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Searched refs:CLK_TOP_PCIE0_MCU_SEL (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt7629-clk.h112 #define CLK_TOP_PCIE0_MCU_SEL 102 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7629-clk.h116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7629.c527 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents,
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c408 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15),