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Searched refs:CLK_TOP_NFI2X_SEL (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c540 MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15),
647 GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
685 GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5),
/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h106 #define CLK_TOP_NFI2X_SEL 96 macro
H A Dmt2712-clk.h153 #define CLK_TOP_NFI2X_SEL 122 macro
H A Dmt2701-clk.h111 #define CLK_TOP_NFI2X_SEL 100 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h125 #define CLK_TOP_NFI2X_SEL 111 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2712.c683 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x0a0, 0, 4, 7),
H A Dclk-mt8365.c508 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
H A Dclk-mt2701.c541 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,