Home
last modified time | relevance | path

Searched refs:CLK_TOP_MUX_MSDC30_1 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h28 #define CLK_TOP_MUX_MSDC30_1 18 macro
H A Dmt8183-clk.h45 #define CLK_TOP_MUX_MSDC30_1 9 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6797.c348 MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
H A Dclk-mt8183.c500 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183-kukui.dtsi388 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
H A Dmt8183.dtsi1564 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,