Searched refs:CLK_TOP_MSDCPLL (Results 1 – 17 of 17) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 45 #define CLK_TOP_MSDCPLL 34 macro
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| H A D | mt6765-clk.h | 74 #define CLK_TOP_MSDCPLL 39 macro
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| H A D | mt8173-clk.h | 47 #define CLK_TOP_MSDCPLL 37 macro
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| H A D | mediatek,mt8365-clk.h | 63 #define CLK_TOP_MSDCPLL 53 macro
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| H A D | mt2712-clk.h | 110 #define CLK_TOP_MSDCPLL 79 macro
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| H A D | mt2701-clk.h | 47 #define CLK_TOP_MSDCPLL 37 macro
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| H A D | mt8192-clk.h | 136 #define CLK_TOP_MSDCPLL 124 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 64 #define CLK_TOP_MSDCPLL 51 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 398 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
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| H A D | clk-mt8173-topckgen.c | 477 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
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| H A D | clk-mt2712.c | 117 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
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| H A D | clk-mt8365.c | 84 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
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| H A D | clk-mt8192.c | 82 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
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| H A D | clk-mt6765.c | 124 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
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| H A D | clk-mt2701.c | 96 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 139 FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
241 CLK_TOP_MSDCPLL,
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8365-evk.dts | 142 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
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