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Searched refs:CLK_TOP_DXCC_SEL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt6765-clk.h152 #define CLK_TOP_DXCC_SEL 117 macro
H A Dmediatek,mt8365-clk.h94 #define CLK_TOP_DXCC_SEL 84 macro
H A Dmt8192-clk.h54 #define CLK_TOP_DXCC_SEL 42 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8365.c475 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
H A Dclk-mt8192.c646 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
H A Dclk-mt6765.c438 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,