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Searched refs:CLK_TOP_A1SYS_HP_SEL (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt7622-clk.h82 #define CLK_TOP_A1SYS_HP_SEL 70 macro
H A Dmt2712-clk.h172 #define CLK_TOP_A1SYS_HP_SEL 141 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7622.c420 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
H A Dclk-mt2712.c713 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmt8195-afe-pcm.yaml168 <&topckgen 100>, //CLK_TOP_A1SYS_HP_SEL
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi689 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
H A Dmt2712e.dtsi289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,