| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | exynos5410.h | 23 #define CLK_SCLK_UART1 129 macro
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| H A D | exynos5250.h | 44 #define CLK_SCLK_UART1 147 macro
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| H A D | exynos7-clk.h | 38 #define CLK_SCLK_UART1 4 macro
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| H A D | exynos4.h | 65 #define CLK_SCLK_UART1 152 macro
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| H A D | exynos5420.h | 30 #define CLK_SCLK_UART1 129 macro
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| H A D | exynos3250.h | 254 #define CLK_SCLK_UART1 246 macro
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| H A D | exynos5433.h | 430 #define CLK_SCLK_UART1 35 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | exynos7420-clk.h | 41 #define CLK_SCLK_UART1 4 macro
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | exynos7420.dtsi | 51 <&clock_top0 CLK_SCLK_UART1>,
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-exynos5410.c | 217 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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| H A D | clk-exynos5250.c | 496 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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| H A D | clk-exynos3250.c | 570 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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| H A D | clk-exynos7.c | 363 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
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| H A D | clk-exynos4.c | 783 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
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| H A D | clk-exynos5420.c | 984 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
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| H A D | clk-exynos5433.c | 1743 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
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| /openbmc/linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5410.dtsi | 347 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| H A D | exynos3250.dtsi | 694 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
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| H A D | exynos4.dtsi | 463 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| H A D | exynos5250.dtsi | 1194 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| H A D | exynos5420.dtsi | 1317 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| /openbmc/linux/arch/arm64/boot/dts/exynos/ |
| H A D | exynos7.dtsi | 222 <&clock_top0 CLK_SCLK_UART1>,
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| H A D | exynos5433.dtsi | 1434 <&cmu_peric CLK_SCLK_UART1>;
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