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Searched refs:CLK_SCLK_UART0 (Results 1 – 25 of 25) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dexynos5410.h22 #define CLK_SCLK_UART0 128 macro
H A Dexynos5250.h43 #define CLK_SCLK_UART0 146 macro
H A Dexynos7-clk.h37 #define CLK_SCLK_UART0 3 macro
H A Dexynos4.h64 #define CLK_SCLK_UART0 151 macro
H A Dexynos5420.h29 #define CLK_SCLK_UART0 128 macro
H A Dexynos3250.h255 #define CLK_SCLK_UART0 247 macro
H A Dexynos5433.h431 #define CLK_SCLK_UART0 36 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dexynos7420-clk.h40 #define CLK_SCLK_UART0 3 macro
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5410.c215 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
H A Dclk-exynos5250.c494 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
H A Dclk-exynos3250.c572 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
H A Dclk-exynos7.c365 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
H A Dclk-exynos4.c781 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
H A Dclk-exynos5420.c982 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
H A Dclk-exynos5433.c1746 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi340 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
H A Dexynos3250-artik5.dtsi410 assigned-clocks = <&cmu CLK_SCLK_UART0>;
H A Dexynos3250-monk.dts458 assigned-clocks = <&cmu CLK_SCLK_UART0>;
H A Dexynos3250-rinato.dts669 assigned-clocks = <&cmu CLK_SCLK_UART0>;
H A Dexynos3250.dtsi683 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
H A Dexynos4.dtsi452 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
H A Dexynos5250.dtsi1187 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
H A Dexynos5420.dtsi1310 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi211 <&clock_top0 CLK_SCLK_UART0>;
H A Dexynos5433.dtsi1422 <&cmu_peric CLK_SCLK_UART0>;