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Searched refs:CLK_ROOT_ON (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c365 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
367 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
369 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
405 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
411 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
417 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
467 clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | in set_clk_qspi()
504 target = CLK_ROOT_ON | enet1_ref | in set_clk_enet()
509 target = CLK_ROOT_ON | in set_clk_enet()
560 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_enable_bypass()
[all …]
H A Dclock_slice.c611 return (val & CLK_ROOT_ON) ? 1 : 0; in clock_root_enabled()
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c85 target = CLK_ROOT_ON | in enable_usboh3_clk()
536 target = CLK_ROOT_ON | in enable_i2c_clk()
596 target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
601 target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
606 target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
611 target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
616 target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
707 target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_wdog()
994 target = CLK_ROOT_ON | enet1_ref | in set_clk_enet()
1004 target = CLK_ROOT_ON | enet2_ref | in set_clk_enet()
[all …]
H A Dclock_slice.c715 val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT | in clock_root_cfg()
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddr4_init.c40 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in ddr_init()
H A Dlpddr4_init.c48 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in ddr_init()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h472 #define CLK_ROOT_ON BIT(28) macro
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h2080 #define CLK_ROOT_ON 0x10000000 macro