85 		target = CLK_ROOT_ON |  in enable_usboh3_clk()
536 		target = CLK_ROOT_ON |  in enable_i2c_clk()
561 	target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |  in init_clk_esdhc()
566 	target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |  in init_clk_esdhc()
571 	target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |  in init_clk_esdhc()
596 	target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
601 	target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
606 	target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
611 	target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
616 	target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
621 	target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
626 	target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
649 	target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |  in init_clk_weim()
669 	target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
674 	target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
679 	target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
684 	target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
707 	target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_wdog()
728 	target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |  in init_clk_epdc()
860 	target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |  in set_clk_qspi()
880 	target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |  in set_clk_nand()
949 	target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |  in mxs_set_lcdclk()
989 	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |  in set_clk_enet()
994 	target = CLK_ROOT_ON | enet1_ref |  in set_clk_enet()
999 	target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |  in set_clk_enet()
1004 	target = CLK_ROOT_ON | enet2_ref |  in set_clk_enet()
1009 	target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |  in set_clk_enet()
1015 	target = CLK_ROOT_ON |  in set_clk_enet()