Home
last modified time | relevance | path

Searched refs:CLK_BDP_WR_CHANNEL_DI_PXL (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2712-bdp.c41 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
/openbmc/linux/include/dt-bindings/clock/
H A Dmt2712-clk.h394 #define CLK_BDP_WR_CHANNEL_DI_PXL 16 macro