11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e2f744a8Sweiyi.lu@mediatek.com /* 3e2f744a8Sweiyi.lu@mediatek.com * Copyright (c) 2017 MediaTek Inc. 4e2f744a8Sweiyi.lu@mediatek.com * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5e2f744a8Sweiyi.lu@mediatek.com */ 6e2f744a8Sweiyi.lu@mediatek.com 7e2f744a8Sweiyi.lu@mediatek.com #include <linux/clk-provider.h> 8e2f744a8Sweiyi.lu@mediatek.com #include <linux/platform_device.h> 9e2f744a8Sweiyi.lu@mediatek.com 10e2f744a8Sweiyi.lu@mediatek.com #include "clk-mtk.h" 11e2f744a8Sweiyi.lu@mediatek.com #include "clk-gate.h" 12e2f744a8Sweiyi.lu@mediatek.com 13e2f744a8Sweiyi.lu@mediatek.com #include <dt-bindings/clock/mt2712-clk.h> 14e2f744a8Sweiyi.lu@mediatek.com 15e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate_regs bdp_cg_regs = { 16e2f744a8Sweiyi.lu@mediatek.com .set_ofs = 0x100, 17e2f744a8Sweiyi.lu@mediatek.com .clr_ofs = 0x100, 18e2f744a8Sweiyi.lu@mediatek.com .sta_ofs = 0x100, 19e2f744a8Sweiyi.lu@mediatek.com }; 20e2f744a8Sweiyi.lu@mediatek.com 214c85e20bSAngeloGioacchino Del Regno #define GATE_BDP(_id, _name, _parent, _shift) \ 224c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &bdp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 23e2f744a8Sweiyi.lu@mediatek.com 24e2f744a8Sweiyi.lu@mediatek.com static const struct mtk_gate bdp_clks[] = { 25e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0), 26e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1), 27e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2), 28e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3), 29e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4), 30e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5), 31e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9), 32e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10), 33e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11), 34e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12), 35e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13), 36e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14), 37e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15), 38e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16), 39e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17), 40e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18), 41e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19), 42e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20), 43e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21), 44e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22), 45e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23), 46e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24), 47e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25), 48e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26), 49e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27), 50e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28), 51e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29), 52e2f744a8Sweiyi.lu@mediatek.com GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30), 53e2f744a8Sweiyi.lu@mediatek.com }; 54e2f744a8Sweiyi.lu@mediatek.com 55f3e4e735SMiles Chen static const struct mtk_clk_desc bdp_desc = { 56f3e4e735SMiles Chen .clks = bdp_clks, 57f3e4e735SMiles Chen .num_clks = ARRAY_SIZE(bdp_clks), 58f3e4e735SMiles Chen }; 59e2f744a8Sweiyi.lu@mediatek.com 60e2f744a8Sweiyi.lu@mediatek.com static const struct of_device_id of_match_clk_mt2712_bdp[] = { 61f3e4e735SMiles Chen { 62f3e4e735SMiles Chen .compatible = "mediatek,mt2712-bdpsys", 63f3e4e735SMiles Chen .data = &bdp_desc, 64f3e4e735SMiles Chen }, { 65f3e4e735SMiles Chen /* sentinel */ 66f3e4e735SMiles Chen } 67e2f744a8Sweiyi.lu@mediatek.com }; 6865c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_bdp); 69e2f744a8Sweiyi.lu@mediatek.com 70e2f744a8Sweiyi.lu@mediatek.com static struct platform_driver clk_mt2712_bdp_drv = { 71f3e4e735SMiles Chen .probe = mtk_clk_simple_probe, 72*61ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 73e2f744a8Sweiyi.lu@mediatek.com .driver = { 74e2f744a8Sweiyi.lu@mediatek.com .name = "clk-mt2712-bdp", 75e2f744a8Sweiyi.lu@mediatek.com .of_match_table = of_match_clk_mt2712_bdp, 76e2f744a8Sweiyi.lu@mediatek.com }, 77e2f744a8Sweiyi.lu@mediatek.com }; 78164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt2712_bdp_drv); 79a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 80