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Searched refs:CLK_BDP_WR_CHANNEL_DI_DRAM (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2712-bdp.c42 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
/openbmc/linux/include/dt-bindings/clock/
H A Dmt2712-clk.h395 #define CLK_BDP_WR_CHANNEL_DI_DRAM 17 macro