Searched refs:CFGCHIP2_PHY_PLLON (Results 1 – 3 of 3) sorted by relevance
79 #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ macro
117 #define CFGCHIP2_PHY_PLLON BIT(6) macro
388 mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON; in da8xx_usb0_clk48_enable()389 val = CFGCHIP2_PHY_PLLON; in da8xx_usb0_clk48_enable()