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Searched refs:Bank (Results 1 – 25 of 32) sorted by relevance

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/openbmc/u-boot/board/toradex/colibri_imx6/
H A Dpf0100_otp.inc72 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
73 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
74 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
75 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
[all …]
/openbmc/u-boot/board/toradex/apalis_imx6/
H A Dpf0100_otp.inc74 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
75 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
82 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
83 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A DKconfig98 bool "Define Bank 1"
109 bool "Define Bank 2"
120 bool "Define Bank 3"
131 bool "Define Bank 4"
142 bool "Define Bank 5"
153 bool "Define Bank 6"
164 bool "Define Bank 7"
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxl-s905x-khadas-vim.dts132 gpio-line-names = /* Bank GPIOZ */
137 /* Bank GPIOH */
145 /* Bank BOOT */
150 /* Bank CARD */
153 /* Bank GPIODV */
158 /* Bank GPIOX */
168 /* Bank GPIOCLK */
H A Dmeson-gxl-s905x-libretech-cc.dts183 gpio-line-names = /* Bank GPIOZ */
187 /* Bank GPIOH */
195 /* Bank BOOT */
200 /* Bank CARD */
203 /* Bank GPIODV */
209 /* Bank GPIOX */
220 /* Bank GPIOCLK */
H A Dmeson-gxbb-odroidc2.dts201 gpio-line-names = /* Bank GPIOZ */
207 /* Bank GPIOH */
209 /* Bank BOOT */
214 /* Bank CARD */
217 /* Bank GPIODV */
222 /* Bank GPIOY */
227 /* Bank GPIOX */
237 /* Bank GPIOCLK */
H A Dmeson-gxbb-nanopi-k2.dts205 gpio-line-names = /* Bank GPIOZ */
211 /* Bank GPIOH */
214 /* Bank BOOT */
220 /* Bank CARD */
223 /* Bank GPIODV */
228 /* Bank GPIOY */
238 /* Bank GPIOX */
248 /* Bank GPIOCLK */
H A Dam437x-sk-evm.dts81 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
88 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
95 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
102 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
/openbmc/libcper/sections/
H A Dcper-section-memory.c45 json_object_new_uint64(memory_error->Bank)); in cper_section_platform_memory_to_ir()
50 json_object_new_uint64(memory_error->Bank & 0xFF)); in cper_section_platform_memory_to_ir()
53 json_object_new_uint64(memory_error->Bank >> 8)); in cper_section_platform_memory_to_ir()
269 json_object_new_uint64(memory_error->Bank)); in cper_section_platform_memory2_to_ir()
274 json_object_new_uint64(memory_error->Bank & 0xFF)); in cper_section_platform_memory2_to_ir()
277 json_object_new_uint64(memory_error->Bank >> 8)); in cper_section_platform_memory2_to_ir()
483 section_cper->Bank = in ir_section_memory_to_cper()
492 section_cper->Bank = address + (group << 8); in ir_section_memory_to_cper()
613 section_cper->Bank = (UINT16)json_object_get_uint64(obj); in ir_section_memory2_to_cper()
621 section_cper->Bank = address + (group << 8); in ir_section_memory2_to_cper()
/openbmc/u-boot/doc/SPI/
H A Dstatus.txt11 - Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing)
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/
H A D0011-Platform-CS1000-Fix-Bank-offsets.patch4 Subject: [PATCH 9/9] Platform: CS1000: Fix Bank offsets
H A D0012-Platform-CS1000-Increase-BL2-partition-size.patch102 /* Bank configurations */
108 /* Bank : Images flash offsets are with respect to the bank */
H A D0007-Plaform-Corstone1000-Switch-to-metadata-v2.patch84 + /* Bank state: It's not used in corstone1000 at the moment.Currently
/openbmc/u-boot/board/rockchip/evb_rv1108/
H A DREADME28 Bus Width=16 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=512MB
/openbmc/u-boot/doc/
H A DREADME.N121339 - Bank numbers: 1 or 2.
H A DREADME.fsl_iim29 using "Word y of Bank x" from the register summary in 30.3.2. This is
H A DREADME.mpc85xxcds210 Flash Bank 1 @ 0xfe000000
211 Flash Bank 2 @ 0xff000000
/openbmc/u-boot/drivers/mtd/spi/
H A DKconfig86 bool "SPI flash Bank/Extended address register support"
88 Enable the SPI flash Bank/Extended address register support.
89 Bank/Extended address registers are used to access the flash
/openbmc/openbmc/meta-amd/meta-ethanolx/recipes-amd/amd-fpga/files/
H A Dfpgardu.sh226 echo ----------FPGAreg$FPGA_REG-----Switch Bank S1:
271 echo ----------FPGAreg$FPGA_REG-----Switch Bank S2:
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/
H A Dtrusted-firmware-m-corstone1000.inc33 file://0011-Platform-CS1000-Fix-Bank-offsets.patch \
/openbmc/openbmc-test-automation/lib/pdu/
H A Dcyber.robot74 # Bank Number : 2 Outlet Number : 16
/openbmc/u-boot/doc/imx/habv4/guides/
H A Dmx6_mx7_secure_boot.txt234 | Device | Bank and Word | Value |
269 | Device | Bank and Word | Value |
/openbmc/u-boot/Documentation/devicetree/bindings/ram/
H A Dfsl,mpc83xx-mem-controller.txt170 - bank_interleaving_ctrl: Bank (chip select) interleaving control; possible
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.lsch376 ----------------------------------------- ----> 0x5_84D0_0000 | Bank
97 | Debug Server FW (2M) | | Bank
/openbmc/libcper/include/libcper/
H A DCper.h949 UINT16 Bank; member
1025 UINT16 Bank; member

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