1*95d26fc5SJayanth Othayoth#!/bin/bash 2*95d26fc5SJayanth Othayothecho 3*95d26fc5SJayanth Othayothecho "-----FPGA Ethanol<x> CRB Register Dump Utility" 4*95d26fc5SJayanth Othayothecho 5*95d26fc5SJayanth OthayothI2CBUS=2 6*95d26fc5SJayanth OthayothFPGAADDR=0x50 7*95d26fc5SJayanth Othayoth 8*95d26fc5SJayanth Othayoth# FPGA FW Version Information 9*95d26fc5SJayanth OthayothFPGA_REG=39 10*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 11*95d26fc5SJayanth OthayothMAJOR=$((DATA >> 4)) 12*95d26fc5SJayanth OthayothMINOR=$((DATA & 0x0F)) 13*95d26fc5SJayanth Othayothecho FPGA FW Version: $MAJOR.$MINOR 14*95d26fc5SJayanth Othayoth 15*95d26fc5SJayanth Othayoth# IP register information 16*95d26fc5SJayanth OthayothFPGA_REG=0 17*95d26fc5SJayanth OthayothIP_REG_MAX=3 18*95d26fc5SJayanth Othayothprintf "IP Address Registers: " 19*95d26fc5SJayanth Othayothwhile [ $FPGA_REG -le $IP_REG_MAX ] 20*95d26fc5SJayanth Othayoth do 21*95d26fc5SJayanth Othayoth # not using printf as integer and hex values are the same for this use 22*95d26fc5SJayanth Othayoth DATA=$(i2cget -y $I2CBUS $FPGAADDR $FPGA_REG) 23*95d26fc5SJayanth Othayoth if [ $FPGA_REG -ne $IP_REG_MAX ] ; then 24*95d26fc5SJayanth Othayoth printf "%d." "$DATA" 25*95d26fc5SJayanth Othayoth else 26*95d26fc5SJayanth Othayoth printf "%d\n\n" "$DATA" 27*95d26fc5SJayanth Othayoth fi 28*95d26fc5SJayanth Othayoth ((FPGA_REG=FPGA_REG+1)) 29*95d26fc5SJayanth Othayoth done 30*95d26fc5SJayanth Othayoth 31*95d26fc5SJayanth Othayoth# VDD block - Addresses 16 - 23 32*95d26fc5SJayanth OthayothFPGA_REG=16 33*95d26fc5SJayanth OthayothVDD_REG_MAX=23 34*95d26fc5SJayanth OthayothSOCKET=0 35*95d26fc5SJayanth Othayoth 36*95d26fc5SJayanth Othayothwhile [ $FPGA_REG -le $VDD_REG_MAX ] 37*95d26fc5SJayanth Othayoth do 38*95d26fc5SJayanth Othayoth VDD_LOOP_CNT=0 39*95d26fc5SJayanth Othayoth 40*95d26fc5SJayanth Othayoth while [ $VDD_LOOP_CNT -le 1 ] 41*95d26fc5SJayanth Othayoth do 42*95d26fc5SJayanth Othayoth if [ $VDD_LOOP_CNT -eq 0 ] ; then 43*95d26fc5SJayanth Othayoth VDD_LOOP_CNT_TXT="Enables" 44*95d26fc5SJayanth Othayoth else 45*95d26fc5SJayanth Othayoth VDD_LOOP_CNT_TXT="Power Goods" 46*95d26fc5SJayanth Othayoth fi 47*95d26fc5SJayanth Othayoth DATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 48*95d26fc5SJayanth Othayoth echo ----------FPGAreg$FPGA_REG-----P$SOCKET VDD "$VDD_LOOP_CNT_TXT" 49*95d26fc5SJayanth Othayoth echo VDD_18_DUAL : $((DATA & 0x01)) 50*95d26fc5SJayanth Othayoth echo VDD_SOC_DUAL: $(((DATA & 0x02) >> 1)) 51*95d26fc5SJayanth Othayoth echo VDD_SPD_ABCD: $(((DATA & 0x04) >> 2)) 52*95d26fc5SJayanth Othayoth echo VDD_VPP_ABCD: $(((DATA & 0x08) >> 3)) 53*95d26fc5SJayanth Othayoth echo VDD_VTT_ABCD: $(((DATA & 0x10) >> 4)) 54*95d26fc5SJayanth Othayoth echo VDD_MEM_ABCD: $(((DATA & 0x20) >> 5)) 55*95d26fc5SJayanth Othayoth echo VDD_SPD_EFGH: $(((DATA & 0x40) >> 6)) 56*95d26fc5SJayanth Othayoth echo VDD_VPP_EFGH: $(((DATA & 0x80) >> 7)) 57*95d26fc5SJayanth Othayoth 58*95d26fc5SJayanth Othayoth ((FPGA_REG=FPGA_REG+1)) 59*95d26fc5SJayanth Othayoth DATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 60*95d26fc5SJayanth Othayoth echo VDD_VTT_EFGH : $((DATA & 0x01)) 61*95d26fc5SJayanth Othayoth echo VDD_MEM_EFGH : $(((DATA & 0x02) >> 1)) 62*95d26fc5SJayanth Othayoth echo VDD_18_RUN-- : $(((DATA & 0x04) >> 2)) 63*95d26fc5SJayanth Othayoth echo VDD_SOC_RUN- : $(((DATA & 0x08) >> 3)) 64*95d26fc5SJayanth Othayoth echo VDD_CORE_RUN : $(((DATA & 0x10) >> 4)) 65*95d26fc5SJayanth Othayoth ((FPGA_REG=FPGA_REG+1)) 66*95d26fc5SJayanth Othayoth ((VDD_LOOP_CNT=VDD_LOOP_CNT+1)) 67*95d26fc5SJayanth Othayoth done 68*95d26fc5SJayanth Othayoth ((SOCKET=SOCKET+1)) 69*95d26fc5SJayanth Othayoth done 70*95d26fc5SJayanth Othayoth 71*95d26fc5SJayanth Othayoth# Power State/Reset Data 72*95d26fc5SJayanth OthayothFPGA_REG=24 73*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 74*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----Power state Information: 75*95d26fc5SJayanth Othayothecho P0_SLP_S5_L--- : $((DATA & 0x01)) 76*95d26fc5SJayanth Othayothecho P0_SLP_S3_L--- : $(((DATA & 0x02) >> 1)) 77*95d26fc5SJayanth Othayothecho ATX_PS_ON----- : $(((DATA & 0x04) >> 2)) 78*95d26fc5SJayanth Othayothecho FPGA_5_DUAL_EN : $(((DATA & 0x08) >> 3)) 79*95d26fc5SJayanth Othayoth 80*95d26fc5SJayanth Othayoth# Power Good information 81*95d26fc5SJayanth OthayothFPGA_REG=25 82*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 83*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----Power Good Information: 84*95d26fc5SJayanth Othayothecho VDD_33_DUAL_PG------- : $((DATA & 0x01)) 85*95d26fc5SJayanth Othayothecho FPGA_VDD_CORE_DUAL_PG : $(((DATA & 0x02) >> 1)) 86*95d26fc5SJayanth Othayothecho MGMT_VDD_VPP_DUAL_PG- : $(((DATA & 0x04) >> 2)) 87*95d26fc5SJayanth Othayothecho MGMT_VDD_MEM_DUAL_PG- : $(((DATA & 0x08) >> 3)) 88*95d26fc5SJayanth Othayothecho MGMT_VDD_CORE_DUAL_PG : $(((DATA & 0x10) >> 4)) 89*95d26fc5SJayanth Othayothecho ATX_PWR_OK----------- : $(((DATA & 0x20) >> 5)) 90*95d26fc5SJayanth Othayoth 91*95d26fc5SJayanth Othayoth# Power and Reset Signals 92*95d26fc5SJayanth OthayothFPGA_REG=26 93*95d26fc5SJayanth OthayothPWRRST_REG_MAX=27 94*95d26fc5SJayanth OthayothSOCKET=0 95*95d26fc5SJayanth Othayothwhile [ $FPGA_REG -le $PWRRST_REG_MAX ] 96*95d26fc5SJayanth Othayoth do 97*95d26fc5SJayanth Othayoth DATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 98*95d26fc5SJayanth Othayoth echo ----------FPGAreg$FPGA_REG-----P$SOCKET Power and Reset Signals: 99*95d26fc5SJayanth Othayoth echo RSMRST_L----------------- : $((DATA & 0x01)) 100*95d26fc5SJayanth Othayoth echo PWR_GOOD----------------- : $(((DATA & 0x02) >> 1)) 101*95d26fc5SJayanth Othayoth echo PWRGD_OUT---------------- : $(((DATA & 0x04) >> 2)) 102*95d26fc5SJayanth Othayoth echo FPGA_PWROK_RESET_BUF_EN_L : $(((DATA & 0x08) >> 3)) 103*95d26fc5SJayanth Othayoth echo 33_PWROK----------------- : $(((DATA & 0x10) >> 4)) 104*95d26fc5SJayanth Othayoth echo VDD_CORE_RUN_PWROK------- : $(((DATA & 0x20) >> 5)) 105*95d26fc5SJayanth Othayoth echo VDD_SOC_RUN_PWROK-------- : $(((DATA & 0x40) >> 6)) 106*95d26fc5SJayanth Othayoth echo 33_RESET_L--------------- : $(((DATA & 0x80) >> 7)) 107*95d26fc5SJayanth Othayoth ((FPGA_REG=FPGA_REG+1)) 108*95d26fc5SJayanth Othayoth done 109*95d26fc5SJayanth Othayoth 110*95d26fc5SJayanth Othayoth# Processor and power cable preset signals 111*95d26fc5SJayanth OthayothFPGA_REG=28 112*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 113*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----Processor and power cable preset signals: 114*95d26fc5SJayanth Othayothecho P0_PRESENT_L--------------------- : $((DATA & 0x01)) 115*95d26fc5SJayanth Othayothecho P0_VDD_MEM_ABCD_12_RUN_PLUG_PRSNT : $(((DATA & 0x02) >> 1)) 116*95d26fc5SJayanth Othayothecho P0_VDD_MEM_EFGH_12_RUN_PLUG_PRSNT : $(((DATA & 0x04) >> 2)) 117*95d26fc5SJayanth Othayothecho P0_VDD_12_RUN_PLUG_PRSNT--------- : $(((DATA & 0x08) >> 3)) 118*95d26fc5SJayanth Othayothecho P1_PRESENT_L--------------------- : $(((DATA & 0x10) >> 4)) 119*95d26fc5SJayanth Othayothecho P1_VDD_MEM_ABCD_12_RUN_PLUG_PRSNT : $(((DATA & 0x20) >> 5)) 120*95d26fc5SJayanth Othayothecho P1_VDD_MEM_EFGH_12_RUN_PLUG_PRSNT : $(((DATA & 0x40) >> 6)) 121*95d26fc5SJayanth Othayothecho P1_VDD_12_RUN_PLUG_PRSNT--------- : $(((DATA & 0x80) >> 7)) 122*95d26fc5SJayanth Othayoth 123*95d26fc5SJayanth Othayoth# Board LEDs 124*95d26fc5SJayanth OthayothFPGA_REG=29 125*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 126*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----LED States: 127*95d26fc5SJayanth Othayothecho PWR_GOOD_LED--- : $((DATA & 0x01)) 128*95d26fc5SJayanth Othayothecho PWROK_LED------ : $(((DATA & 0x02) >> 1)) 129*95d26fc5SJayanth Othayothecho RESET_LED_L---- : $(((DATA & 0x04) >> 2)) 130*95d26fc5SJayanth Othayothecho P0_PROCHOT_LED- : $(((DATA & 0x08) >> 3)) 131*95d26fc5SJayanth Othayothecho P1_PROCHOT_LED- : $(((DATA & 0x10) >> 4)) 132*95d26fc5SJayanth Othayoth 133*95d26fc5SJayanth Othayoth# VR thermal errors 134*95d26fc5SJayanth OthayothFPGA_REG=30 135*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 136*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----VR Thermal Errors: 137*95d26fc5SJayanth Othayothecho P0_VDD_MEM_ABCD_SUS_VRHOT_L : $((DATA & 0x01)) 138*95d26fc5SJayanth Othayothecho P0_VDD_MEM_EFGH_SUS_VRHOT_L : $(((DATA & 0x02) >> 1)) 139*95d26fc5SJayanth Othayothecho P0_VDD_SOC_RUN_VRHOT_L----- : $(((DATA & 0x04) >> 2)) 140*95d26fc5SJayanth Othayothecho P0_VDD_CORE_RUN_VRHOT_L---- : $(((DATA & 0x08) >> 3)) 141*95d26fc5SJayanth Othayothecho P1_VDD_MEM_ABCD_SUS_VRHOT_L : $(((DATA & 0x10) >> 4)) 142*95d26fc5SJayanth Othayothecho P1_VDD_MEM_EFGH_SUS_VRHOT_L : $(((DATA & 0x20) >> 5)) 143*95d26fc5SJayanth Othayothecho P1_VDD_SOC_RUN_VRHOT_L----- : $(((DATA & 0x40) >> 6)) 144*95d26fc5SJayanth Othayothecho P1_VDD_CORE_RUN_VRHOT_L---- : $(((DATA & 0x80) >> 7)) 145*95d26fc5SJayanth Othayoth 146*95d26fc5SJayanth Othayoth# Processor and board Thermal Errors 147*95d26fc5SJayanth OthayothFPGA_REG=31 148*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 149*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----Processor and board Thermal Errors: 150*95d26fc5SJayanth Othayothecho FPGA_P0_THERMTRIP_L : $((DATA & 0x01)) 151*95d26fc5SJayanth Othayothecho FPGA_P1_THERMTRIP_L : $(((DATA & 0x02) >> 1)) 152*95d26fc5SJayanth Othayothecho SENSOR_THERM_L----- : $(((DATA & 0x04) >> 2)) 153*95d26fc5SJayanth Othayothecho P0_PROCHOT_L------- : $(((DATA & 0x08) >> 3)) 154*95d26fc5SJayanth Othayothecho P1_PROCHOT_L------- : $(((DATA & 0x10) >> 4)) 155*95d26fc5SJayanth Othayoth 156*95d26fc5SJayanth Othayoth# AST2500 control Signals 157*95d26fc5SJayanth OthayothFPGA_REG=32 158*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 159*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----AST2500 Control Signals: 160*95d26fc5SJayanth Othayothecho MGMT_ASSERT_BMC_READY--- : $((DATA & 0x01)) 161*95d26fc5SJayanth Othayothecho MGMT_ASSERT_LOCAL_LOCK-- : $(((DATA & 0x02) >> 1)) 162*95d26fc5SJayanth Othayothecho MGMT_ASSERT_PWR_BTN----- : $(((DATA & 0x04) >> 2)) 163*95d26fc5SJayanth Othayothecho MGMT_ASSERT_RST_BTN----- : $(((DATA & 0x08) >> 3)) 164*95d26fc5SJayanth Othayothecho MGMT_ASSERT_NMI_BTN----- : $(((DATA & 0x10) >> 4)) 165*95d26fc5SJayanth Othayothecho MGMT_ASSERT_P0_PROCHOT-- : $(((DATA & 0x20) >> 5)) 166*95d26fc5SJayanth Othayothecho MGMT_ASSERT_P1_PROCHOT-- : $(((DATA & 0x40) >> 6)) 167*95d26fc5SJayanth Othayothecho MGMT_ASSERT_WARM_RST_BTN : $(((DATA & 0x80) >> 7)) 168*95d26fc5SJayanth Othayoth 169*95d26fc5SJayanth Othayoth# FPGA processor control signals 170*95d26fc5SJayanth OthayothFPGA_REG=33 171*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 172*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----FPGA processor Control Signals: 173*95d26fc5SJayanth Othayothecho ASSERT_P0_PWROK_L-------- : $((DATA & 0x01)) 174*95d26fc5SJayanth Othayothecho ASSERT_P0_RESET_L-------- : $(((DATA & 0x02) >> 1)) 175*95d26fc5SJayanth Othayothecho ASSERT_P0_PROCHOT_L------ : $(((DATA & 0x04) >> 2)) 176*95d26fc5SJayanth Othayothecho MGMT_SYS_MON_P0_PROCHOT_L : $(((DATA & 0x08) >> 3)) 177*95d26fc5SJayanth Othayothecho ASSERT_P1_PWROK_L-------- : $(((DATA & 0x10) >> 4)) 178*95d26fc5SJayanth Othayothecho ASSERT_P1_RESET_L-------- : $(((DATA & 0x20) >> 5)) 179*95d26fc5SJayanth Othayothecho ASSERT_P1_PROCHOT_L------ : $(((DATA & 0x40) >> 6)) 180*95d26fc5SJayanth Othayothecho MGMT_SYS_MON_P1_PROCHOT_L : $(((DATA & 0x80) >> 7)) 181*95d26fc5SJayanth Othayoth 182*95d26fc5SJayanth Othayoth# Buttons/Resets 183*95d26fc5SJayanth OthayothFPGA_REG=34 184*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 185*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----Button and Reset Signals: 186*95d26fc5SJayanth Othayothecho PWR_BTN_L----- : $((DATA & 0x01)) 187*95d26fc5SJayanth Othayothecho RST_BTN_L----- : $(((DATA & 0x02) >> 1)) 188*95d26fc5SJayanth Othayothecho WARM_RST_BTN_L : $(((DATA & 0x04) >> 2)) 189*95d26fc5SJayanth Othayothecho NMI_BTN_L----- : $(((DATA & 0x08) >> 3)) 190*95d26fc5SJayanth Othayothecho FPGA_BTN_L---- : $(((DATA & 0x10) >> 4)) 191*95d26fc5SJayanth Othayothecho P0_PWR_BTN_L-- : $(((DATA & 0x20) >> 5)) 192*95d26fc5SJayanth Othayothecho P0_SYS_RESET_L : $(((DATA & 0x40) >> 6)) 193*95d26fc5SJayanth Othayothecho P0_KBRST_L---- : $(((DATA & 0x80) >> 7)) 194*95d26fc5SJayanth Othayoth 195*95d26fc5SJayanth Othayoth# Miscellaneous Block 1 196*95d26fc5SJayanth OthayothFPGA_REG=35 197*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 198*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----Miscellaneous 35 Signals: 199*95d26fc5SJayanth Othayothecho MGMT_AC_LOSS_L---------- : $((DATA & 0x01)) 200*95d26fc5SJayanth Othayothecho P0_NV_FORCE_SELF_REFRESH : $(((DATA & 0x02) >> 1)) 201*95d26fc5SJayanth Othayothecho P1_NV_FORCE_SELF_REFRESH : $(((DATA & 0x04) >> 2)) 202*95d26fc5SJayanth Othayothecho P0_LOCAL_SPI_ROM_SEL_L-- : $(((DATA & 0x08) >> 3)) 203*95d26fc5SJayanth Othayothecho PCIE_SLOT4_HP_FON_L----- : $(((DATA & 0x10) >> 4)) 204*95d26fc5SJayanth Othayothecho P0_NMI_SYNC_FLOOD_L----- : $(((DATA & 0x20) >> 5)) 205*95d26fc5SJayanth Othayothecho FPGA_LPC_RST_L---------- : $(((DATA & 0x40) >> 6)) 206*95d26fc5SJayanth Othayothecho MGMT_SMBUS_ALERT_L------ : $(((DATA & 0x80) >> 7)) 207*95d26fc5SJayanth Othayoth 208*95d26fc5SJayanth Othayoth# Miscellaneous Block 2 209*95d26fc5SJayanth OthayothFPGA_REG=36 210*95d26fc5SJayanth OthayothSHUTDOWNERR=0 211*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 212*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----Miscellaneous 36 Signals: 213*95d26fc5SJayanth Othayothecho physical_pg------------------- : $((DATA & 0x01)) 214*95d26fc5SJayanth Othayothecho shutdown_error---------------- : $(((DATA & 0x02) >> 1)) 215*95d26fc5SJayanth OthayothSHUTDOWNERR=$(((DATA & 0x02) >> 1)) 216*95d26fc5SJayanth Othayothecho P0_PRESENT_HDT---------------- : $(((DATA & 0x04) >> 2)) 217*95d26fc5SJayanth Othayothecho P1_PRESENT_HDT---------------- : $(((DATA & 0x08) >> 3)) 218*95d26fc5SJayanth Othayothecho DAP_EXT_P0_CORE_RUN_VOLTAGE_PG : $(((DATA & 0x10) >> 4)) 219*95d26fc5SJayanth Othayothecho FPGA_BRD_ID------------------- : $(((DATA & 0x20) >> 5)) 220*95d26fc5SJayanth Othayothecho FPGA_BRD_ID------------------- : $(((DATA & 0x40) >> 6)) 221*95d26fc5SJayanth Othayothecho MGMT_FPGA_RSVD---------------- : $(((DATA & 0x80) >> 7)) 222*95d26fc5SJayanth Othayoth 223*95d26fc5SJayanth Othayoth# Switch S1 224*95d26fc5SJayanth OthayothFPGA_REG=37 225*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 226*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----Switch Bank S1: 227*95d26fc5SJayanth Othayothif [ $((DATA & 0x01)) -eq 1 ] ; then 228*95d26fc5SJayanth Othayoth echo "FPGA_SW1-1 - OFF - P0 PwrReg PU with Proc" 229*95d26fc5SJayanth Othayothelse 230*95d26fc5SJayanth Othayoth echo "FPGA_SW1-1 - ON - P0 PwrReg PU without Proc" 231*95d26fc5SJayanth Othayothfi 232*95d26fc5SJayanth Othayothif [ $(((DATA & 0x02) >> 1)) -eq 1 ] ; then 233*95d26fc5SJayanth Othayoth echo "FPGA_SW1-1 - OFF - P1 PwrReg PU with Proc" 234*95d26fc5SJayanth Othayothelse 235*95d26fc5SJayanth Othayoth echo "FPGA_SW1-1 - ON - P1 PwrReg PU without Proc" 236*95d26fc5SJayanth Othayothfi 237*95d26fc5SJayanth Othayothif [ $(((DATA & 0x04) >> 2)) -eq 1 ] ; then 238*95d26fc5SJayanth Othayoth echo "FPGA_SW1-3 - OFF - ATX Connectors Valid" 239*95d26fc5SJayanth Othayothelse 240*95d26fc5SJayanth Othayoth echo "FPGA_SW1-3 - ON - ATX Connectors Ignored" 241*95d26fc5SJayanth Othayothfi 242*95d26fc5SJayanth Othayothif [ $(((DATA & 0x08) >> 3)) -eq 1 ] ; then 243*95d26fc5SJayanth Othayoth echo "FPGA_SW1-4 - OFF - Wait for BMC Boot" 244*95d26fc5SJayanth Othayothelse 245*95d26fc5SJayanth Othayoth echo "FPGA_SW1-4 - ON - Do Not Wait for BMC Boot" 246*95d26fc5SJayanth Othayothfi 247*95d26fc5SJayanth Othayothif [ $(((DATA & 0x10) >> 4)) -eq 1 ] ; then 248*95d26fc5SJayanth Othayoth echo "FPGA_SW1-5 - OFF - MemPwrReg PU after ATX" 249*95d26fc5SJayanth Othayothelse 250*95d26fc5SJayanth Othayoth echo "FPGA_SW1-5 - ON - MemPwrReg PU before ATX" 251*95d26fc5SJayanth Othayothfi 252*95d26fc5SJayanth Othayothif [ $(((DATA & 0x20) >> 5)) -eq 1 ] ; then 253*95d26fc5SJayanth Othayoth echo "FPGA_SW1-6 - OFF - DAP CORE Reg Bypass DISABLED" 254*95d26fc5SJayanth Othayothelse 255*95d26fc5SJayanth Othayoth echo "FPGA_SW1-6 - ON - DAP CORE Reg Bypass ENABLED" 256*95d26fc5SJayanth Othayothfi 257*95d26fc5SJayanth Othayothif [ $(((DATA & 0x40) >> 6)) -eq 1 ] ; then 258*95d26fc5SJayanth Othayoth echo "FPGA_SW1-7 - OFF - Bypass P0 in HDT JTAG Chain DISABLED" 259*95d26fc5SJayanth Othayothelse 260*95d26fc5SJayanth Othayoth echo "FPGA_SW1-7 - ON - Bypass P0 in HDT JTAG Chain ENABLED" 261*95d26fc5SJayanth Othayothfi 262*95d26fc5SJayanth Othayothif [ $(((DATA & 0x80) >> 7)) -eq 1 ] ; then 263*95d26fc5SJayanth Othayoth echo "FPGA_SW1-8 - OFF - Bypass P1 in HDT JTAG Chain DISABLED" 264*95d26fc5SJayanth Othayothelse 265*95d26fc5SJayanth Othayoth echo "FPGA_SW1-8 - ON - Bypass P1 in HDT JTAG Chain ENABLED" 266*95d26fc5SJayanth Othayothfi 267*95d26fc5SJayanth Othayoth 268*95d26fc5SJayanth Othayoth# Switch S2 269*95d26fc5SJayanth OthayothFPGA_REG=38 270*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 271*95d26fc5SJayanth Othayothecho ----------FPGAreg$FPGA_REG-----Switch Bank S2: 272*95d26fc5SJayanth Othayothif [ $((DATA & 0x01)) -eq 1 ] ; then 273*95d26fc5SJayanth Othayoth echo "FPGA_SW2-1 - OFF - Boot from SPI ROM behind BMC" 274*95d26fc5SJayanth Othayothelse 275*95d26fc5SJayanth Othayoth echo "FPGA_SW2-1 - ON - Boot from P0 local SPI ROM" 276*95d26fc5SJayanth Othayothfi 277*95d26fc5SJayanth Othayothif [ $(((DATA & 0x02) >> 1)) -eq 1 ] ; then 278*95d26fc5SJayanth Othayoth echo "FPGA_SW2-2 - OFF - PCIe SLOT4 hot plug forced PwrON without driver" 279*95d26fc5SJayanth Othayothelse 280*95d26fc5SJayanth Othayoth echo "FPGA_SW2-2 - ON - PCIe SLOT4 hot plug NOT forced PwrON without driver" 281*95d26fc5SJayanth Othayothfi 282*95d26fc5SJayanth Othayothif [ $(((DATA & 0x04) >> 2)) -eq 1 ] ; then 283*95d26fc5SJayanth Othayoth echo "FPGA_SW2-3 - OFF - SMI testing DISABLED" 284*95d26fc5SJayanth Othayothelse 285*95d26fc5SJayanth Othayoth echo "FPGA_SW2-3 - ON - SMI testing ENABLED" 286*95d26fc5SJayanth Othayothfi 287*95d26fc5SJayanth Othayothif [ $(((DATA & 0x08) >> 3)) -eq 1 ] ; then 288*95d26fc5SJayanth Othayoth echo "FPGA_SW2-4 - OFF - PROCHOT testing DISABLED" 289*95d26fc5SJayanth Othayothelse 290*95d26fc5SJayanth Othayoth echo "FPGA_SW2-4 - ON - PROCHOT testing ENABLED" 291*95d26fc5SJayanth Othayothfi 292*95d26fc5SJayanth Othayothif [ $(((DATA & 0x10) >> 4)) -eq 1 ] ; then 293*95d26fc5SJayanth Othayoth echo "FPGA_SW2-5 - OFF - PwrCycle on post code C0 DISABLED" 294*95d26fc5SJayanth Othayothelse 295*95d26fc5SJayanth Othayoth echo "FPGA_SW2-5 - ON - PwrCycle on post code C0 ENABLED" 296*95d26fc5SJayanth Othayothfi 297*95d26fc5SJayanth Othayothif [ $(((DATA & 0x20) >> 5)) -eq 1 ] ; then 298*95d26fc5SJayanth Othayoth echo "FPGA_SW2-6 - OFF - PwrCycle Px DISABLED" 299*95d26fc5SJayanth Othayothelse 300*95d26fc5SJayanth Othayoth echo "FPGA_SW2-6 - ON - PwrCycle - Px Present - RESET_L | Px Not Present VR PwrGood" 301*95d26fc5SJayanth Othayothfi 302*95d26fc5SJayanth Othayothif [ $(((DATA & 0x40) >> 6)) -eq 1 ] ; then 303*95d26fc5SJayanth Othayoth echo "FPGA_SW2-7 - OFF - BMC IP Address display DISABLED" 304*95d26fc5SJayanth Othayothelse 305*95d26fc5SJayanth Othayoth echo "FPGA_SW2-7 - ON - BMC IP Address display ENABLED" 306*95d26fc5SJayanth Othayothfi 307*95d26fc5SJayanth Othayothif [ $(((DATA & 0x80) >> 7)) -eq 1 ] ; then 308*95d26fc5SJayanth Othayoth echo "FPGA_SW1-8 - OFF - FORCE_SELFREFRESH support diabled" 309*95d26fc5SJayanth Othayothelse 310*95d26fc5SJayanth Othayoth echo "FPGA_SW1-8 - ON - FORCE_SELFREFRESH support diabled" 311*95d26fc5SJayanth Othayothfi 312*95d26fc5SJayanth Othayoth 313*95d26fc5SJayanth Othayoth# Powerup Error Group 314*95d26fc5SJayanth Othayothecho ------------------------Power and Thermal Error Group 315*95d26fc5SJayanth Othayothif [ $SHUTDOWNERR = 0 ] ; then 316*95d26fc5SJayanth Othayoth echo NO Shutdown Errors Detected 317*95d26fc5SJayanth Othayothfi 318*95d26fc5SJayanth Othayoth 319*95d26fc5SJayanth OthayothFPGA_REG=40 320*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 321*95d26fc5SJayanth Othayothif [ $((DATA & 0x0F)) != 0 ] ; then 322*95d26fc5SJayanth Othayoth echo PU Error: PU1$((DATA & 0x0F)) 323*95d26fc5SJayanth Othayoth echo "$DATA" 324*95d26fc5SJayanth Othayothfi 325*95d26fc5SJayanth Othayoth 326*95d26fc5SJayanth OthayothFPGA_REG=41 327*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 328*95d26fc5SJayanth Othayothif [ $((DATA & 0x07)) != 0 ] ; then 329*95d26fc5SJayanth Othayoth echo PU Error: PU2$((DATA & 0x07)) 330*95d26fc5SJayanth Othayothfi 331*95d26fc5SJayanth Othayoth 332*95d26fc5SJayanth OthayothFPGA_REG=42 333*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 334*95d26fc5SJayanth Othayothif [ $((DATA & 0x0F)) != 0 ] ; then 335*95d26fc5SJayanth Othayoth echo PU Error: PU1$((DATA & 0x0F)) 336*95d26fc5SJayanth Othayothfi 337*95d26fc5SJayanth Othayoth 338*95d26fc5SJayanth OthayothFPGA_REG=43 339*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 340*95d26fc5SJayanth Othayothif [ $((DATA & 0x07)) != 0 ] ; then 341*95d26fc5SJayanth Othayoth echo PU Error: PU4$((DATA & 0x07)) 342*95d26fc5SJayanth Othayothfi 343*95d26fc5SJayanth Othayoth 344*95d26fc5SJayanth OthayothFPGA_REG=44 345*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 346*95d26fc5SJayanth Othayothif [ $((DATA & 0x03)) != 0 ] ; then 347*95d26fc5SJayanth Othayoth echo PU Error: PU5$((DATA & 0x03)) 348*95d26fc5SJayanth Othayothfi 349*95d26fc5SJayanth Othayoth 350*95d26fc5SJayanth OthayothFPGA_REG=45 351*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 352*95d26fc5SJayanth Othayothif [ $((DATA & 0x07)) != 0 ] ; then 353*95d26fc5SJayanth Othayoth echo PU Error: PU6$((DATA & 0x07)) 354*95d26fc5SJayanth Othayothfi 355*95d26fc5SJayanth Othayoth 356*95d26fc5SJayanth Othayoth# Powerdown Error Group 357*95d26fc5SJayanth OthayothFPGA_REG=46 358*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 359*95d26fc5SJayanth Othayothif [ $((DATA & 0x0F)) != 0 ] ; then 360*95d26fc5SJayanth Othayoth echo PD Error: PD1$((DATA & 0x0F)) 361*95d26fc5SJayanth Othayothfi 362*95d26fc5SJayanth Othayoth 363*95d26fc5SJayanth OthayothFPGA_REG=47 364*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 365*95d26fc5SJayanth Othayothif [ $((DATA & 0x07)) != 0 ] ; then 366*95d26fc5SJayanth Othayoth echo PD Error: PD2$((DATA & 0x07)) 367*95d26fc5SJayanth Othayothfi 368*95d26fc5SJayanth Othayoth 369*95d26fc5SJayanth OthayothFPGA_REG=48 370*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 371*95d26fc5SJayanth Othayothif [ $((DATA & 0x0F)) != 0 ] ; then 372*95d26fc5SJayanth Othayoth echo PD Error: PD3$((DATA & 0x0F)) 373*95d26fc5SJayanth Othayothfi 374*95d26fc5SJayanth Othayoth 375*95d26fc5SJayanth OthayothFPGA_REG=49 376*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 377*95d26fc5SJayanth Othayothif [ $((DATA & 0x07)) != 0 ] ; then 378*95d26fc5SJayanth Othayoth echo PD Error: PD4$((DATA & 0x07)) 379*95d26fc5SJayanth Othayothfi 380*95d26fc5SJayanth Othayoth 381*95d26fc5SJayanth OthayothFPGA_REG=50 382*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 383*95d26fc5SJayanth Othayothif [ $((DATA & 0x03)) != 0 ] ; then 384*95d26fc5SJayanth Othayoth echo PD Error: PD5$((DATA & 0x03)) 385*95d26fc5SJayanth Othayothfi 386*95d26fc5SJayanth Othayoth 387*95d26fc5SJayanth OthayothFPGA_REG=51 388*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 389*95d26fc5SJayanth Othayothif [ $((DATA & 0x03)) != 0 ] ; then 390*95d26fc5SJayanth Othayoth echo PD Error: PD6$((DATA & 0x03)) 391*95d26fc5SJayanth Othayothfi 392*95d26fc5SJayanth Othayoth 393*95d26fc5SJayanth OthayothFPGA_REG=52 394*95d26fc5SJayanth OthayothDATA=$(i2cget -y $I2CBUS $FPGAADDR "$(printf "0x%x" $FPGA_REG)") 395*95d26fc5SJayanth Othayothif [ $((DATA & 0x0F)) != 0 ] ; then 396*95d26fc5SJayanth Othayoth echo Thermal Error: H_0$((DATA & 0x0F)) 397*95d26fc5SJayanth Othayothfi 398*95d26fc5SJayanth Othayothecho ------------- end of data ----------------- 399