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Searched refs:BUS_CNTL (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/video/fbdev/aty/
H A Dmach64_gx.c274 aty_st_le32(BUS_CNTL, 0x890e20f1, par); in aty_set_dac_ATI68860_B()
327 aty_st_le32(BUS_CNTL, 0x890e20f1, par); in aty_set_dac_ATT21C498()
887 aty_st_le32(BUS_CNTL, 0x890e20f1, par); in aty_set_dac_unsupported()
890 aty_st_le32(BUS_CNTL, 0x590e10ff, par); in aty_set_dac_unsupported()
H A Dmach64_accel.c51 aty_st_le32(BUS_CNTL, in aty_reset_engine()
52 aty_ld_le32(BUS_CNTL, par) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK, par); in aty_reset_engine()
H A Datyfb_base.c1437 aty_st_le32(BUS_CNTL, 0x680000f9, par); in atyfb_set_par()
1440 aty_st_le32(BUS_CNTL, 0x680000f9, par); in atyfb_set_par()
1443 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par); in atyfb_set_par()
1447 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par); in atyfb_set_par()
2136 aty_st_le32(BUS_CNTL, in aty_resume_chip()
2137 aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par); in aty_resume_chip()
2601 aty_ld_le32(BUS_CNTL, par), in aty_init()
2627 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | in aty_init()
H A Dradeon_pm.c601 rinfo->save_regs[36] = INREG(BUS_CNTL); in radeon_pm_save_regs()
1733 OUTREG(BUS_CNTL, rinfo->save_regs[36]); in radeon_reinitialize_M10()
1987 OUTREG(BUS_CNTL, rinfo->save_regs[36]); in radeon_reinitialize_M9P()
2224 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
H A Daty128fb.c2015 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); in aty128_init()
/openbmc/linux/include/video/
H A Daty128.h16 #define BUS_CNTL 0x0030 macro
H A Dmach64.h149 #define BUS_CNTL 0x00A0 /* Dword offset 0_28 */ macro
H A Dradeon.h11 #define BUS_CNTL 0x0030 macro
/openbmc/qemu/hw/display/
H A Dati_regs.h34 #define BUS_CNTL 0x0030 macro
H A Dati.c301 case BIOS_0_SCRATCH ... BUS_CNTL - 1: in ati_mm_read()
558 case BIOS_0_SCRATCH ... BUS_CNTL - 1: in ati_mm_write()
/openbmc/u-boot/include/
H A Dradeon.h10 #define BUS_CNTL 0x0030 macro
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dr600d.h710 #define BUS_CNTL 0x5420 macro
H A Dr600.c1857 tmp = RREG32(BUS_CNTL); in r600_gpu_pci_config_reset()
1859 WREG32(BUS_CNTL, tmp); in r600_gpu_pci_config_reset()