Searched refs:BR2 (Results 1 – 9 of 9) sorted by relevance
| /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/ |
| H A D | Kconfig | 112 hex "Preliminary value for BR2"
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | fsl_lbc.h | 20 #define BR2 0x5010 macro
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| /openbmc/u-boot/include/ |
| H A D | ppc_asm.tmpl | 107 #define BR2 0x00000110
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | nanomips_translate.c.inc | 191 /* P.BR2 instruction pool */
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| /openbmc/u-boot/ |
| H A D | README | 3137 Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
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| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | xtensa-modules.c.inc | 1710 { "BR2", "b", REGFILE_BR, 2, 8 },
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| /openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/ |
| H A D | xtensa-modules.c.inc | 9204 { "BR2", "b", REGFILE_BR, 2, 8 },
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| /openbmc/qemu/target/xtensa/core-test_kc705_be/ |
| H A D | xtensa-modules.c.inc | 10781 { "BR2", "b", REGFILE_BR, 2, 8 },
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| /openbmc/qemu/target/xtensa/core-dsp3400/ |
| H A D | xtensa-modules.c.inc | 41034 { "BR2", "b", REGFILE_BR, 2, 8 },
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