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Searched refs:BCM2836_NCORES (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/include/hw/intc/
H A Dbcm2836_control.h23 #define BCM2836_NCORES 4 macro
36 uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
40 uint32_t timercontrol[BCM2836_NCORES];
41 uint32_t mailboxcontrol[BCM2836_NCORES];
45 uint8_t timerirqs[BCM2836_NCORES];
53 uint32_t irqsrc[BCM2836_NCORES];
54 uint32_t fiqsrc[BCM2836_NCORES];
57 qemu_irq irq[BCM2836_NCORES];
58 qemu_irq fiq[BCM2836_NCORES];
/openbmc/qemu/hw/intc/
H A Dbcm2836_control.c83 for (i = 0; i < BCM2836_NCORES; i++) { in bcm2836_control_update()
89 assert(s->route_gpu_irq < BCM2836_NCORES); in bcm2836_control_update()
112 for (i = 0; i < BCM2836_NCORES; i++) { in bcm2836_control_update()
134 for (i = 0; i < BCM2836_NCORES; i++) { in bcm2836_control_update()
145 assert(core >= 0 && core < BCM2836_NCORES); in bcm2836_control_set_local_irq()
326 for (i = 0; i < BCM2836_NCORES; i++) { in bcm2836_control_reset()
347 BCM2836_NCORES); in bcm2836_control_init()
349 BCM2836_NCORES); in bcm2836_control_init()
351 BCM2836_NCORES); in bcm2836_control_init()
353 BCM2836_NCORES); in bcm2836_control_init()
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