1cc28296dSAndrew Baumann /* 2cc28296dSAndrew Baumann * Raspberry Pi emulation (c) 2012 Gregory Estrade 3cc28296dSAndrew Baumann * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4cc28296dSAndrew Baumann * 5cc28296dSAndrew Baumann * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6cc28296dSAndrew Baumann * Written by Andrew Baumann 7cc28296dSAndrew Baumann * 867d80321SZoltán Baldaszti * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti 967d80321SZoltán Baldaszti * Added basic IRQ_TIMER interrupt support 1067d80321SZoltán Baldaszti * 116111a0c0SPhilippe Mathieu-Daudé * This work is licensed under the terms of the GNU GPL, version 2 or later. 126111a0c0SPhilippe Mathieu-Daudé * See the COPYING file in the top-level directory. 13cc28296dSAndrew Baumann */ 14cc28296dSAndrew Baumann 15cc28296dSAndrew Baumann #ifndef BCM2836_CONTROL_H 16cc28296dSAndrew Baumann #define BCM2836_CONTROL_H 17cc28296dSAndrew Baumann 18cc28296dSAndrew Baumann #include "hw/sysbus.h" 1967d80321SZoltán Baldaszti #include "qemu/timer.h" 20db1015e9SEduardo Habkost #include "qom/object.h" 21cc28296dSAndrew Baumann 22cc28296dSAndrew Baumann /* 4 mailboxes per core, for 16 total */ 23cc28296dSAndrew Baumann #define BCM2836_NCORES 4 24cc28296dSAndrew Baumann #define BCM2836_MBPERCORE 4 25cc28296dSAndrew Baumann 26cc28296dSAndrew Baumann #define TYPE_BCM2836_CONTROL "bcm2836-control" 27*8063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(BCM2836ControlState, BCM2836_CONTROL) 28cc28296dSAndrew Baumann 29db1015e9SEduardo Habkost struct BCM2836ControlState { 30cc28296dSAndrew Baumann /*< private >*/ 31cc28296dSAndrew Baumann SysBusDevice busdev; 32cc28296dSAndrew Baumann /*< public >*/ 33cc28296dSAndrew Baumann MemoryRegion iomem; 34cc28296dSAndrew Baumann 35cc28296dSAndrew Baumann /* mailbox state */ 36cc28296dSAndrew Baumann uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE]; 37cc28296dSAndrew Baumann 38cc28296dSAndrew Baumann /* interrupt routing/control registers */ 39cc28296dSAndrew Baumann uint8_t route_gpu_irq, route_gpu_fiq; 40cc28296dSAndrew Baumann uint32_t timercontrol[BCM2836_NCORES]; 41cc28296dSAndrew Baumann uint32_t mailboxcontrol[BCM2836_NCORES]; 42cc28296dSAndrew Baumann 43cc28296dSAndrew Baumann /* interrupt status regs (derived from input pins; not visible to user) */ 44cc28296dSAndrew Baumann bool gpu_irq, gpu_fiq; 45cc28296dSAndrew Baumann uint8_t timerirqs[BCM2836_NCORES]; 46cc28296dSAndrew Baumann 4767d80321SZoltán Baldaszti /* local timer */ 4867d80321SZoltán Baldaszti QEMUTimer timer; 4967d80321SZoltán Baldaszti uint32_t local_timer_control; 5067d80321SZoltán Baldaszti uint8_t route_localtimer; 5167d80321SZoltán Baldaszti 52cc28296dSAndrew Baumann /* interrupt source registers, post-routing (also input-derived; visible) */ 53cc28296dSAndrew Baumann uint32_t irqsrc[BCM2836_NCORES]; 54cc28296dSAndrew Baumann uint32_t fiqsrc[BCM2836_NCORES]; 55cc28296dSAndrew Baumann 56cc28296dSAndrew Baumann /* outputs to CPU cores */ 57cc28296dSAndrew Baumann qemu_irq irq[BCM2836_NCORES]; 58cc28296dSAndrew Baumann qemu_irq fiq[BCM2836_NCORES]; 59db1015e9SEduardo Habkost }; 60cc28296dSAndrew Baumann 61cc28296dSAndrew Baumann #endif 62