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Searched refs:BASE_DEVCPU_GCB (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/
H A Dgpio.c14 val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0)); in mscc_gpio_set_alternate()
15 val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1)); in mscc_gpio_set_alternate()
31 writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0)); in mscc_gpio_set_alternate()
32 writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1)); in mscc_gpio_set_alternate()
H A Dreset.c37 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
55 (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
65 writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
H A Dphy.c30 writel(data, BASE_DEVCPU_GCB + MIIM_MII_CMD(miimdev)); in mscc_phy_rd_wr()
39 data = readl(BASE_DEVCPU_GCB + MIIM_MII_STATUS(miimdev)); in mscc_phy_rd_wr()
44 data = readl(BASE_DEVCPU_GCB + MIIM_MII_DATA(miimdev)); in mscc_phy_rd_wr()
/openbmc/u-boot/board/mscc/ocelot/
H A Docelot.c30 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in mscc_switch_reset()
32 if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST, in mscc_switch_reset()
40 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); in mscc_switch_reset()
41 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); in mscc_switch_reset()
/openbmc/u-boot/board/mscc/jr2/
H A Djr2.c42 reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0); in vcoreiii_gpio_set_alternate()
43 reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1); in vcoreiii_gpio_set_alternate()
47 reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0); in vcoreiii_gpio_set_alternate()
48 reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1); in vcoreiii_gpio_set_alternate()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot.h22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71070000) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval.h22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71070000) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2.h22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71010000) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt.h22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71010000) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton.h22 #define BASE_DEVCPU_GCB ((void __iomem *)0x60070000) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h408 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); in hal_vcoreiii_ddr_reset_assert()
409 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR); in hal_vcoreiii_ddr_reset_assert()
416 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); in hal_vcoreiii_ddr_reset_release()
417 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); in hal_vcoreiii_ddr_reset_release()
432 clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); in hal_vcoreiii_ddr_failed()
/openbmc/u-boot/board/mscc/luton/
H A Dluton.c41 u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF; in do_board_detect()