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Searched refs:AR934X_SRIF_CPU_DPLL1_REG (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c193 ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif); in ar934x_pll_init()
/openbmc/linux/arch/mips/ath79/
H A Dclock.c257 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); in ar934x_clocks_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h1123 #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 macro
/openbmc/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h990 #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 macro