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Searched refs:AR934X_PLL_DDR_CONFIG_REG (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c179 pll_regs + AR934X_PLL_DDR_CONFIG_REG); in ar934x_pll_init()
269 ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG); in ar934x_update_clock()
/openbmc/linux/arch/mips/ath79/
H A Dclock.c292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h351 #define AR934X_PLL_DDR_CONFIG_REG 0x04 macro
/openbmc/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h314 #define AR934X_PLL_DDR_CONFIG_REG 0x04 macro