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Searched refs:AR71XX_DDR_REG_TAP_CTRL1 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dddr.c183 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
227 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
275 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
331 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c299 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
405 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
425 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
468 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dddr.c136 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); in ar934x_ddr_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h215 #define AR71XX_DDR_REG_TAP_CTRL1 0x20 macro