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Searched refs:AR71XX_DDR_REG_CONTROL (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dddr.c123 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
129 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
134 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
140 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
146 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
158 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
164 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
169 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
198 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
204 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c254 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
262 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
270 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
274 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
288 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
301 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
352 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
360 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
378 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
386 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dddr.c69 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
72 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
98 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
104 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
111 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
120 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
123 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
129 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h211 #define AR71XX_DDR_REG_CONTROL 0x10 macro