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Searched refs:APLL_MODE_MASK (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3036.c86 GPLL_MODE_MASK | APLL_MODE_MASK, in rkclk_init()
163 GPLL_MODE_MASK | APLL_MODE_MASK, in rkclk_init()
181 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, in rkclk_pll_get_rate()
H A Dclk_rk322x.c87 GPLL_MODE_MASK | APLL_MODE_MASK, in rkclk_init()
164 GPLL_MODE_MASK | APLL_MODE_MASK, in rkclk_init()
182 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, in rkclk_pll_get_rate()
H A Dclk_rk3188.c198 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
218 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
240 switch ((con >> shift) & APLL_MODE_MASK) { in rkclk_pll_get_rate()
H A Dclk_rk3128.c148 GPLL_MODE_MASK | APLL_MODE_MASK, in rkclk_init()
225 GPLL_MODE_MASK | APLL_MODE_MASK | CPLL_MODE_MASK, in rkclk_init()
250 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, in rkclk_pll_get_rate()
H A Dclk_rk3288.c498 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rk3288_clk_configure_cpu()
532 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rk3288_clk_configure_cpu()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h170 APLL_MODE_MASK = 3, enumerator
H A Dcru_rk3036.h97 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, enumerator
H A Dcru_rk322x.h104 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, enumerator
H A Dcru_rk3128.h106 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, enumerator
H A Dcru_rk3288.h204 APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT, enumerator