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Searched refs:APCS_CPU_PWR_CTL (Results 1 – 1 of 1) sorted by relevance

/openbmc/linux/arch/arm/mach-qcom/
H A Dplatsmp.c26 #define APCS_CPU_PWR_CTL 0x04 macro
104 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
112 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
114 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
118 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
123 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
125 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
177 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
179 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
184 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
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