26 #define APCS_CPU_PWR_CTL	0x04  macro
104 	writel(reg_val, reg + APCS_CPU_PWR_CTL);  in cortex_a7_release_secondary()
112 	writel(reg_val, reg + APCS_CPU_PWR_CTL);  in cortex_a7_release_secondary()
114 	writel(reg_val, reg + APCS_CPU_PWR_CTL);  in cortex_a7_release_secondary()
118 	writel(reg_val, reg + APCS_CPU_PWR_CTL);  in cortex_a7_release_secondary()
123 	writel(reg_val, reg + APCS_CPU_PWR_CTL);  in cortex_a7_release_secondary()
125 	writel(reg_val, reg + APCS_CPU_PWR_CTL);  in cortex_a7_release_secondary()
177 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
179 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
184 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
189 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
194 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
199 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
280 	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);  in kpssv2_release_secondary()
285 	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);  in kpssv2_release_secondary()
290 	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);  in kpssv2_release_secondary()
294 	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);  in kpssv2_release_secondary()