Searched refs:AHCI_PHYCS1R (Results 1 – 2 of 2) sorted by relevance
10 #define AHCI_PHYCS1R 0x00c4 macro25 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); in sunxi_ahci_phy_init()29 clrsetbits_le32(reg_base + AHCI_PHYCS1R, in sunxi_ahci_phy_init()32 setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); in sunxi_ahci_phy_init()33 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); in sunxi_ahci_phy_init()
39 #define AHCI_PHYCS1R 0x00c4 macro95 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()99 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, in ahci_sunxi_phy_init()102 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); in ahci_sunxi_phy_init()103 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()