Searched refs:ACPI_BASE_ADDRESS (Results 1 – 7 of 7) sorted by relevance
68 ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in power_state_get()69 ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); in power_state_get()70 ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in power_state_get()71 ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS); in power_state_get()72 ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS); in power_state_get()73 ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0)); in power_state_get()74 ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1)); in power_state_get()77 ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0)); in power_state_get()78 ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1)); in power_state_get()79 ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2)); in power_state_get()[all …]
45 dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1); in broadwell_pch_early_init()90 clrsetio_32(ACPI_BASE_ADDRESS + PM1_CNT, SLP_TYP, SCI_EN); in pch_misc_init()135 outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); in enable_all_gpe()136 outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); in enable_all_gpe()137 outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); in enable_all_gpe()138 outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); in enable_all_gpe()
46 pei_data->pmbase = ACPI_BASE_ADDRESS; in broadwell_fill_pei_data()
21 u16 pmbase = ACPI_BASE_ADDRESS; in acpi_create_fadt()183 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in chipset_prev_sleep_state()184 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in chipset_prev_sleep_state()203 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in chipset_clear_sleep_state()204 outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); in chipset_clear_sleep_state()
41 #define ACPI_BASE_ADDRESS 0x400 macro
36 #define ACPI_BASE_ADDRESS 0x1000 macro
82 #define ACPI_BASE_ADDRESS 0x0400 macro