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Searched refs:A15 (Results 1 – 25 of 66) sorted by relevance

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/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts257 /* A15 PLL 0 reference clock */
266 /* A15 PLL 1 reference clock */
338 /* A15 CPU core voltage */
341 regulator-name = "A15 Vcore";
345 label = "A15 Vcore";
360 /* Total current for the two A15 cores */
363 label = "A15 Icore";
381 /* Total power for the two A15 cores */
384 label = "A15 Pcore";
395 /* Total energy for the two A15 cores */
[all …]
H A Dvexpress-v2p-ca15-tc1.dts6 * Cortex-A15 MPCore (V2P-CA15)
/openbmc/linux/arch/arm/include/debug/
H A Dexynos.S23 teq \tmp, #0xf0 @@ A15
27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
/openbmc/qemu/docs/system/arm/
H A Dhighbank.rst8 which has four Cortex-A15 cores.
H A Dcpu-features.rst10 Cortex-A15 and the Cortex-A57, which respectively implement Arm
12 implement PMUs. For example, if a user wants to use a Cortex-A15 without
20 ``aarch64`` CPU property. A CPU type such as the Cortex-A15, which does
102 (5) Let's try probing CPU features for the Cortex-A15 CPU type::
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420-cpus.dtsi9 * boards: CPU[0123] being the A15.
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
H A Dexynos5422-odroidxu3.dts27 /* A15 cluster: VDD_ARM */
H A Dexynos5422-odroidxu3-lite.dts39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
H A Dexynos5422-cpus.dtsi13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
/openbmc/linux/Documentation/devicetree/bindings/hwmon/
H A Dvexpress.txt22 label = "A15 Jcore";
/openbmc/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts6 * Cortex-A15 MPCore (V2P-CA15)
/openbmc/linux/arch/arm/mach-hisi/
H A DKconfig37 bool "Hisilicon HiP04 Cortex A15 family"
/openbmc/linux/Documentation/arch/arm/keystone/
H A Doverview.rst7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
/openbmc/linux/arch/arm/mach-exynos/
H A DKconfig67 Samsung Exynos5 (Cortex-A15/A7) SoC based systems
/openbmc/u-boot/arch/arm/mach-exynos/
H A DKconfig33 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7a/
H A Dtune-cortexa15.inc5 TUNEVALID[cortexa15] = "Enable Cortex-A15 specific processor optimizations"
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-boneblue.dts124 …AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0…
459 "WIFI_LED", /* A15 */
/openbmc/linux/Documentation/arch/arm/
H A Dsunxi.rst123 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S132 moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
/openbmc/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g5.c584 #define A15 71 macro
592 SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1);
593 SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC);
594 PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO);
596 FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
597 FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
598 FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
599 FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
1908 ASPEED_PINCTRL_PIN(A15),
2527 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24),
[all …]
H A Dpinctrl-aspeed-g6.c578 #define A15 71 macro
579 SIG_EXPR_LIST_DECL_SESG(A15, BMCINT, BMCINT, SIG_DESC_SET(SCU418, 7));
580 SIG_EXPR_LIST_DECL_SESG(A15, SIOSCI, SIOSCI, SIG_DESC_SET(SCU4B8, 7));
581 PIN_DECL_2(A15, GPIOI7, BMCINT, SIOSCI);
582 FUNC_GROUP_DECL(BMCINT, A15);
583 FUNC_GROUP_DECL(SIOSCI, A15);
1645 ASPEED_PINCTRL_PIN(A15),
2418 ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7),
H A Dpinctrl-aspeed-g4.c334 #define A15 35 macro
335 SIG_EXPR_LIST_DECL_SINGLE(A15, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
338 SIG_EXPR_LIST_DECL_DUAL(A15, GPIE2OUT, GPIE2, GPIE);
339 PIN_DECL_2(A15, GPIOE3, NRI3, GPIE2OUT);
341 FUNC_GROUP_DECL(NRI3, A15);
342 FUNC_GROUP_DECL(GPIE2, B15, A15);
1914 ASPEED_PINCTRL_PIN(A15),
2539 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25),
/openbmc/u-boot/arch/arm/dts/
H A Dstm32429i-eval-u-boot.dtsi203 <STM32_PINMUX('G', 5, AF12)>, /* A15-BA1 */
/openbmc/linux/drivers/soc/tegra/
H A DKconfig75 Tegra124's "4+1" Cortex-A15 CPU complex.
/openbmc/linux/arch/arm/crypto/
H A DKconfig183 Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode

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