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/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_shift.S7 \prefix\()_ver \dst, \v, \imm
37 .macro slli_ver dst, v, imm
55 .if (\imm)
88 movi a2, \imm
95 movi a2, 32 - \imm
116 movi a2, \imm
123 movi a2, \imm
146 movi a2, \imm
153 movi a2, \imm
176 movi a2, \imm
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H A Dtest_sar.S5 .macro test_sar prefix, imm
6 \prefix\()_set \imm
7 \prefix\()_ver \imm
22 .macro sar_set imm
23 movi a2, \imm
27 .macro sar_ver imm
37 .macro ssr_set imm
38 movi a2, \imm
42 .macro ssr_ver imm
52 .macro ssl_set imm
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/openbmc/linux/arch/powerpc/net/
H A Dbpf_jit_comp32.c305 s32 imm = insn[i].imm; in bpf_jit_build_body() local
367 imm = -imm; in bpf_jit_build_body()
380 imm = -imm; in bpf_jit_build_body()
436 imm = ilog2(imm); in bpf_jit_build_body()
488 imm = ilog2((u32)imm); in bpf_jit_build_body()
496 imm = -imm; in bpf_jit_build_body()
514 imm = -imm; in bpf_jit_build_body()
521 imm = ilog2(imm); in bpf_jit_build_body()
1198 if (imm >= 0 && imm < 32768) { in bpf_jit_build_body()
1217 if (imm >= 0 && imm < 65536) { in bpf_jit_build_body()
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H A Dbpf_jit_comp64.c384 s32 imm = insn[i].imm; in bpf_jit_build_body() local
428 if (!imm) { in bpf_jit_build_body()
430 } else if (imm >= -32768 && imm < 32768) { in bpf_jit_build_body()
439 if (!imm) { in bpf_jit_build_body()
441 } else if (imm > -32768 && imm <= 32768) { in bpf_jit_build_body()
457 if (imm >= -32768 && imm < 32768) in bpf_jit_build_body()
489 if (imm == 0) in bpf_jit_build_body()
642 if (imm < 0) in bpf_jit_build_body()
1147 if (imm >= 0 && imm < 32768) { in bpf_jit_build_body()
1178 if (imm >= -32768 && imm < 32768) { in bpf_jit_build_body()
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/openbmc/linux/arch/arm/net/
H A Dbpf_jit_32.h170 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
173 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument
177 #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm) argument
180 #define ARM_BIC_I(rd, rn, imm) _AL3_I(ARM_INST_BIC, rd, rn, imm) argument
187 #define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm) argument
190 #define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm) argument
219 #define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm) argument
237 #define ARM_ORR_I(rd, rn, imm) _AL3_I(ARM_INST_ORR, rd, rn, imm) argument
251 #define ARM_RSB_I(rd, rn, imm) _AL3_I(ARM_INST_RSB, rd, rn, imm) argument
253 #define ARM_RSC_I(rd, rn, imm) _AL3_I(ARM_INST_RSC, rd, rn, imm) argument
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/openbmc/linux/arch/loongarch/kernel/
H A Dinst.c86 imm = insn.reg2i16_format.immediate; in simu_branch()
256 u32 larch_insn_gen_break(int imm) in larch_insn_gen_break() argument
260 if (imm < 0 || imm >= SZ_32K) { in larch_insn_gen_break()
265 emit_break(&insn, imm); in larch_insn_gen_break()
288 if (imm < -SZ_512K || imm >= SZ_512K) { in larch_insn_gen_lu12iw()
293 emit_lu12iw(&insn, rd, imm); in larch_insn_gen_lu12iw()
302 if (imm < -SZ_512K || imm >= SZ_512K) { in larch_insn_gen_lu32id()
307 emit_lu32id(&insn, rd, imm); in larch_insn_gen_lu32id()
316 if (imm < -SZ_2K || imm >= SZ_2K) { in larch_insn_gen_lu52id()
321 emit_lu52id(&insn, rd, rj, imm); in larch_insn_gen_lu52id()
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/openbmc/linux/tools/include/linux/
H A Dfilter.h40 .imm = 0 })
48 .imm = 0 })
58 .imm = IMM })
66 .imm = IMM })
76 .imm = LEN })
86 .imm = 0 })
94 .imm = 0 })
160 .imm = 0 })
170 .imm = 0 })
216 .imm = 0 })
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/openbmc/qemu/target/rx/
H A Dinsns.decode25 &ri rd imm
27 &rri rd imm rs2
29 &mi rs ld mi imm
91 # ADC #imm, rd
113 # AND #imm, rd
125 # BCLR #imm, rs
222 # DIV #imm, rd
431 # MVTIPL #imm
448 # OR #imm, rd
476 # RACW #imm
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/openbmc/linux/samples/bpf/
H A Dbpf_insn.h16 .imm = 0 })
24 .imm = 0 })
34 .imm = IMM })
42 .imm = IMM })
52 .imm = 0 })
60 .imm = 0 })
70 .imm = IMM })
125 .imm = 0 })
135 .imm = 0 })
181 .imm = 0 })
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/openbmc/linux/arch/mips/net/
H A Dbpf_jit_comp.c194 if (imm >= -0x8000 && imm <= 0x7fff) { in emit_mov_i()
224 return imm >= -0x8000 && imm <= 0x7fff; in valid_alu_i()
229 return imm >= -0x7fff && imm <= 0x8000; in valid_alu_i()
234 return imm >= 0 && imm <= 0xffff; in valid_alu_i()
237 return imm == 0 || (imm > 0 && is_power_of_2(imm)); in valid_alu_i()
272 imm = ilog2(abs(imm)); in rewrite_alu_i()
282 imm = ilog2(imm); in rewrite_alu_i()
288 imm--; in rewrite_alu_i()
515 return imm >= 0 && imm <= 0xffff; in valid_jmp_i()
521 return imm >= -0x8000 && imm <= 0x7fff; in valid_jmp_i()
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H A Dbpf_jit_comp32.c177 if (imm < 0) in emit_mov_se_i64()
210 if (imm > S32_MIN && imm < 0) in emit_alu_i64()
214 imm = -imm; in emit_alu_i64()
218 imm = -imm; in emit_alu_i64()
231 if (imm < 0) in emit_alu_i64()
239 if (imm < 0) in emit_alu_i64()
245 if (imm < 0) in emit_alu_i64()
1105 if (imm >= -0x7fff && imm <= 0x8000) { in emit_jmp_i64()
1471 s32 imm = insn->imm; in build_insn() local
1577 if (imm) in build_insn()
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/openbmc/qemu/target/riscv/
H A Dinsn16.decode57 &i imm rs1 rd !extern
58 &s imm rs1 rs2 !extern
59 &j imm rd !extern
60 &b imm rs2 rs1 !extern
61 &u imm rd !extern
79 @cj ... ........... .. &j imm=%imm_cj
82 @c_lqsp ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd
88 @c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd
89 @c_lui ... . ..... ..... .. &u imm=%imm_lui %rd
90 @c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd
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/openbmc/linux/tools/testing/selftests/bpf/
H A Ddisasm.c23 insn->imm >= 0 && insn->imm < __BPF_FUNC_MAX_ID && in __func_get_name()
24 func_id_str[insn->imm]) in __func_get_name()
145 insn->imm, insn->dst_reg); in print_bpf_end_insn()
202 insn->imm); in print_bpf_insn()
212 (insn->imm == BPF_ADD || insn->imm == BPF_AND || in print_bpf_insn()
213 insn->imm == BPF_OR || insn->imm == BPF_XOR)) { in print_bpf_insn()
255 insn->off, insn->imm); in print_bpf_insn()
277 insn->imm); in print_bpf_insn()
288 u64 imm = ((u64)(insn + 1)->imm << 32) | (u32)insn->imm; in print_bpf_insn() local
294 imm = 0; in print_bpf_insn()
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/openbmc/linux/kernel/bpf/
H A Ddisasm.c23 insn->imm >= 0 && insn->imm < __BPF_FUNC_MAX_ID && in __func_get_name()
24 func_id_str[insn->imm]) in __func_get_name()
145 insn->imm, insn->dst_reg); in print_bpf_end_insn()
202 insn->imm); in print_bpf_insn()
212 (insn->imm == BPF_ADD || insn->imm == BPF_AND || in print_bpf_insn()
213 insn->imm == BPF_OR || insn->imm == BPF_XOR)) { in print_bpf_insn()
255 insn->off, insn->imm); in print_bpf_insn()
277 insn->imm); in print_bpf_insn()
288 u64 imm = ((u64)(insn + 1)->imm << 32) | (u32)insn->imm; in print_bpf_insn() local
294 imm = 0; in print_bpf_insn()
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/openbmc/qemu/target/avr/
H A Ddisas.c137 INSN(SUBI, "r%d, %d", a->rd, a->imm)
139 INSN(SBCI, "r%d, %d", a->rd, a->imm)
142 INSN(ANDI, "r%d, %d", a->rd, a->imm)
144 INSN(ORI, "r%d, %d", a->rd, a->imm)
156 INSN(DES, "%d", a->imm)
161 INSN(RJMP, ".%+d", a->imm * 2)
164 INSN(JMP, "0x%x", a->imm * 2)
165 INSN(RCALL, ".%+d", a->imm * 2)
168 INSN(CALL, "0x%x", a->imm * 2)
174 INSN(CPI, "r%d, %d", a->rd, a->imm)
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/openbmc/linux/arch/riscv/net/
H A Dbpf_jit.h266 u32 imm; in rv_j_insn() local
291 u32 imm; in rv_ci_insn() local
329 u32 imm; in rv_cb_insn() local
608 u32 imm; in rvc_addi4spn() local
645 u32 imm; in rvc_addi16sp() local
699 u32 imm; in rvc_lwsp() local
727 u32 imm; in rvc_swsp() local
894 u32 imm; in rvc_ldsp() local
902 u32 imm; in rvc_sdsp() local
940 if (rvc_enabled() && rd == RV_REG_SP && rd == rs && is_10b_int(imm) && imm && !(imm & 0xf)) in emit_addi()
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H A Dbpf_jit_comp32.c130 if (imm >= 0) in emit_imm32()
260 if (imm >= 0) in emit_alu_i64()
270 if (imm < 0) in emit_alu_i64()
280 if (imm < 0) in emit_alu_i64()
284 if (imm >= 32) { in emit_alu_i64()
297 if (imm >= 32) { in emit_alu_i64()
310 if (imm >= 32) { in emit_alu_i64()
962 s32 imm = insn->imm; in bpf_jit_emit_insn() local
1076 switch (imm) { in bpf_jit_emit_insn()
1101 switch (imm) { in bpf_jit_emit_insn()
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/openbmc/linux/arch/arm64/net/
H A Dbpf_jit.h77 #define A64_STRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, STORE) argument
78 #define A64_LDRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, LOAD) argument
79 #define A64_LDRSBI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 8, SIGNED_LOAD) argument
80 #define A64_STRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, STORE) argument
81 #define A64_LDRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, LOAD) argument
83 #define A64_STR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, STORE) argument
84 #define A64_LDR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, LOAD) argument
86 #define A64_STR64I(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 64, STORE) argument
87 #define A64_LDR64I(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 64, LOAD) argument
269 u64 imm64 = (sf) ? (u64)imm : (u64)(u32)imm; \
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/openbmc/qemu/target/arm/tcg/
H A Dt16.decode25 &s_rri_rot !extern s rn rd imm rot
29 &ri !extern rd imm
31 &i !extern imm
33 &ldst_ri !extern p w u rn rt imm
37 &ci !extern cond imm
88 @ldst_ri_1 ..... imm:5 rn:3 rt:3 \
91 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
102 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
111 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
151 @addsub_2i ....... imm:3 rn:3 rd:3 \
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/openbmc/linux/arch/arm/probes/kprobes/
H A Dcheckers-common.c34 int imm = insn & 0xff; in checker_stack_use_imm_0xx() local
35 asi->stack_space = imm; in checker_stack_use_imm_0xx()
47 int imm = insn & 0xff; in checker_stack_use_t32strd() local
48 asi->stack_space = imm << 2; in checker_stack_use_t32strd()
56 int imm = ((insn & 0xf00) >> 4) + (insn & 0xf); in checker_stack_use_imm_x0x() local
57 asi->stack_space = imm; in checker_stack_use_imm_x0x()
66 int imm = insn & 0xfff; in checker_stack_use_imm_xxx() local
67 asi->stack_space = imm; in checker_stack_use_imm_xxx()
/openbmc/qemu/hw/mips/
H A Dbootloader.c112 insn = deposit32(insn, 0, 16, imm); in bl_gen_i_type()
162 bl_gen_i_type(p, 0x0f, 0, rt, imm); in bl_gen_lui()
180 bl_gen_i_type(p, 0x0d, rs, rt, imm); in bl_gen_ori()
219 bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); in bl_gen_li()
222 bl_gen_lui(p, rt, extract32(imm, 16, 16)); in bl_gen_li()
223 bl_gen_ori(p, rt, rt, extract32(imm, 0, 16)); in bl_gen_li()
229 bl_gen_li(p, rt, extract64(imm, 32, 32)); in bl_gen_dli()
231 bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); in bl_gen_dli()
233 bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); in bl_gen_dli()
239 bl_gen_dli(p, rt, imm); /* 64bit */ in bl_gen_load_ulong()
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/openbmc/qemu/tests/qemu-iotests/
H A D026.out6 Event: l1_update; errno: 5; imm: off; once: on; write
11 Event: l1_update; errno: 5; imm: off; once: on; write -b
16 Event: l1_update; errno: 5; imm: off; once: off; write
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
30 Event: l1_update; errno: 28; imm: off; once: on; write
40 Event: l1_update; errno: 28; imm: off; once: off; write
54 Event: l2_load; errno: 5; imm: off; once: on; write
62 Event: l2_load; errno: 5; imm: off; once: on; write -b
70 Event: l2_load; errno: 5; imm: off; once: off; write
86 Event: l2_load; errno: 28; imm: off; once: on; write
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H A D026.out.nocache6 Event: l1_update; errno: 5; imm: off; once: on; write
11 Event: l1_update; errno: 5; imm: off; once: on; write -b
16 Event: l1_update; errno: 5; imm: off; once: off; write
23 Event: l1_update; errno: 5; imm: off; once: off; write -b
30 Event: l1_update; errno: 28; imm: off; once: on; write
40 Event: l1_update; errno: 28; imm: off; once: off; write
54 Event: l2_load; errno: 5; imm: off; once: on; write
62 Event: l2_load; errno: 5; imm: off; once: on; write -b
70 Event: l2_load; errno: 5; imm: off; once: off; write
86 Event: l2_load; errno: 28; imm: off; once: on; write
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/openbmc/linux/arch/riscv/kernel/
H A Dalternative.c76 s32 imm; in riscv_alternative_fix_auipc_jalr() local
79 imm = riscv_insn_extract_utype_itype_imm(auipc_insn, jalr_insn); in riscv_alternative_fix_auipc_jalr()
80 imm -= patch_offset; in riscv_alternative_fix_auipc_jalr()
83 riscv_insn_insert_utype_itype_imm(&call[0], &call[1], imm); in riscv_alternative_fix_auipc_jalr()
91 s32 imm; in riscv_alternative_fix_jal() local
94 imm = riscv_insn_extract_jtype_imm(jal_insn); in riscv_alternative_fix_jal()
95 imm -= patch_offset; in riscv_alternative_fix_jal()
98 riscv_insn_insert_jtype_imm(&jal_insn, imm); in riscv_alternative_fix_jal()
134 s32 imm = riscv_insn_extract_jtype_imm(insn); in riscv_alternative_fix_offsets() local
137 if ((alt_ptr + i * sizeof(u32) + imm) >= alt_ptr && in riscv_alternative_fix_offsets()
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/openbmc/linux/arch/loongarch/net/
H A Dbpf_jit.h111 if (imm == 0) { in move_imm()
117 if (is_signed_imm12(imm)) { in move_imm()
123 if (is_unsigned_imm12(imm)) { in move_imm()
129 imm_63_52 = (imm >> 52) & 0xfff; in move_imm()
130 imm_51_0 = imm & 0xfffffffffffff; in move_imm()
137 imm_31_12 = (imm >> 12) & 0xfffff; in move_imm()
141 imm_11_0 = imm & 0xfff; in move_imm()
145 if (!is_signed_imm32(imm)) { in move_imm()
152 imm_51_31 = (imm >> 31) & 0x1fffff; in move_imm()
155 imm_51_32 = (imm >> 32) & 0xfffff; in move_imm()
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