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/openbmc/qemu/fpu/
H A Dsoftfloat.c130 static inline void name(soft_t *a, float_status *s) \
132 if (unlikely(soft_t ## _is_denormal(*a))) { \
133 *a = soft_t ## _set_sign(soft_t ## _zero, \
134 soft_t ## _is_neg(*a)); \
144 static inline void name(soft_t *a, float_status *s) \ in GEN_INPUT_FLUSH__NOCHECK()
149 soft_t ## _input_flush__nocheck(a, s); \ in GEN_INPUT_FLUSH__NOCHECK()
157 static inline void name(soft_t *a, soft_t *b, float_status *s) \
162 soft_t ## _input_flush__nocheck(a, s); \
171 static inline void name(soft_t *a, soft_t *b, soft_t *c, float_status *s) \
176 soft_t ## _input_flush__nocheck(a, s); \
[all …]
/openbmc/linux/include/linux/
H A Djhash.h35 #define __jhash_mix(a, b, c) \ argument
37 a -= c; a ^= rol32(c, 4); c += b; \
38 b -= a; b ^= rol32(a, 6); a += c; \
39 c -= b; c ^= rol32(b, 8); b += a; \
40 a -= c; a ^= rol32(c, 16); c += b; \
41 b -= a; b ^= rol32(a, 19); a += c; \
42 c -= b; c ^= rol32(b, 4); b += a; \
46 #define __jhash_final(a, b, c) \ argument
49 a ^= c; a -= rol32(c, 11); \
50 b ^= a; b -= rol32(a, 25); \
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/openbmc/linux/tools/testing/selftests/powerpc/include/
H A Dinstructions.h77 #define __PPC_RA(a) (((a) & 0x1f) << 16) argument
98 #define PREFIX_MLS(instr, t, a, r, d) stringify_in_c(.balign 64, , 4;) \ argument
104 __PPC_RA(a) | \
107 #define PREFIX_8LS(instr, t, a, r, d) stringify_in_c(.balign 64, , 4;) \ argument
113 __PPC_RA(a) | \
117 #define PLBZ(t, a, r, d) PREFIX_MLS(PPC_INST_LBZ, t, a, r, d) argument
118 #define PLHZ(t, a, r, d) PREFIX_MLS(PPC_INST_LHZ, t, a, r, d) argument
119 #define PLHA(t, a, r, d) PREFIX_MLS(PPC_INST_LHA, t, a, r, d) argument
120 #define PLWZ(t, a, r, d) PREFIX_MLS(PPC_INST_LWZ, t, a, r, d) argument
121 #define PLWA(t, a, r, d) PREFIX_8LS(0xa4000000, t, a, r, d) argument
[all …]
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvf.c.inc17 * You should have received a copy of the GNU General Public License along with
42 static bool trans_flw(DisasContext *ctx, arg_flw *a)
56 addr = get_address(ctx, a->rs1, a->imm);
57 dest = cpu_fpr[a->rd];
65 static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
78 addr = get_address(ctx, a->rs1, a->imm);
79 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
83 static bool trans_c_flw(DisasContext *ctx, arg_flw *a)
86 return trans_flw(ctx, a);
89 static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a)
[all …]
H A Dtrans_xthead.c.inc15 * You should have received a copy of the GNU General Public License along with
128 arg_th_addsl##SHAMT * a) \
131 return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \
141 static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a)
144 return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
149 static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a)
154 return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
158 static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a,
161 TCGv dest = dest_gpr(ctx, a->rd);
162 TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO);
[all …]
H A Dtrans_rvzfa.c.inc15 * You should have received a copy of the GNU General Public License along with
31 static bool trans_fli_s(DisasContext *ctx, arg_fli_s *a)
37 /* Values below are NaN-boxed to avoid a gen_nanbox_s(). */
73 TCGv_i64 dest = dest_fpr(ctx, a->rd);
74 tcg_gen_movi_i64(dest, fli_s_table[a->rs1]);
75 gen_set_fpr_hs(ctx, a->rd, dest);
81 static bool trans_fli_d(DisasContext *ctx, arg_fli_d *a)
122 TCGv_i64 dest = dest_fpr(ctx, a->rd);
123 tcg_gen_movi_i64(dest, fli_d_table[a->rs1]);
124 gen_set_fpr_d(ctx, a->rd, dest);
[all …]
/openbmc/linux/arch/arm/nwfpe/
H A Dsoftfloat.c113 INLINE bits32 extractFloat32Frac( float32 a ) in extractFloat32Frac() argument
116 return a & 0x007FFFFF; in extractFloat32Frac()
125 INLINE int16 extractFloat32Exp( float32 a ) in extractFloat32Exp() argument
128 return ( a>>23 ) & 0xFF; in extractFloat32Exp()
138 INLINE flag extractFloat32Sign( float32 a )
141 return a>>31;
294 INLINE bits64 extractFloat64Frac( float64 a ) in extractFloat64Frac() argument
297 return a & LIT64( 0x000FFFFFFFFFFFFF ); in extractFloat64Frac()
306 INLINE int16 extractFloat64Exp( float64 a ) in extractFloat64Exp() argument
309 return ( a>>52 ) & 0x7FF; in extractFloat64Exp()
[all …]
/openbmc/qemu/target/hppa/
H A Dtranslate.c1255 static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, in do_add_reg() argument
1260 if (unlikely(is_tc && a->cf == 1)) { in do_add_reg()
1264 if (a->cf) { in do_add_reg()
1267 tcg_r1 = load_gpr(ctx, a->r1); in do_add_reg()
1268 tcg_r2 = load_gpr(ctx, a->r2); in do_add_reg()
1269 do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, in do_add_reg()
1270 is_tsv, is_tc, is_c, a->cf, a->d); in do_add_reg()
1274 static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, in do_add_imm() argument
1279 if (unlikely(is_tc && a->cf == 1)) { in do_add_imm()
1283 if (a->cf) { in do_add_imm()
[all …]
/openbmc/u-boot/arch/mips/include/asm/
H A Daddrspace.h45 #define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) argument
50 #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) argument
51 #define XPHYSADDR(a) ((_ACAST64_(a)) & \ argument
70 #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) argument
71 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) argument
72 #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) argument
73 #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) argument
77 #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) argument
78 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) argument
79 #define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) argument
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Darch-armv8-3a.inc1 DEFAULTTUNE ?= "armv8-3a"
3 TUNEVALID[armv8-3a] = "Enable instructions for ARMv8.3-a"
4 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8-3a', ' -march=armv8.3-a', '', d)…
6 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8-3a', 'armv8-3a:', '', d)}"
10 AVAILTUNES += "armv8-3a armv8-3a-crypto armv8-3a-crypto-sve"
11 ARMPKGARCH:tune-armv8-3a ?= "armv8-3a"
12 ARMPKGARCH:tune-armv8-3a-crypto ?= "armv8-3a"
13 ARMPKGARCH:tune-armv8-3a-crypto-sve ?= "armv8-3a"
14 TUNE_FEATURES:tune-armv8-3a = "aarch64 armv8-3a"
15 TUNE_FEATURES:tune-armv8-3a-crypto = "${TUNE_FEATURES:tune-armv8-3a} crypto"
[all …]
H A Darch-armv8-6a.inc1 DEFAULTTUNE ?= "armv8-6a"
3 TUNEVALID[armv8-6a] = "Enable instructions for ARMv8.6-a"
4 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8-6a', ' -march=armv8.6-a', '', d)…
6 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8-6a', 'armv8-6a:', '', d)}"
10 AVAILTUNES += "armv8-6a armv8-6a-crypto armv8-6a-crypto-sve"
11 ARMPKGARCH:tune-armv8-6a ?= "armv8-6a"
12 ARMPKGARCH:tune-armv8-6a-crypto ?= "armv8-6a"
13 ARMPKGARCH:tune-armv8-6a-crypto-sve ?= "armv8-6a"
14 TUNE_FEATURES:tune-armv8-6a = "aarch64 armv8-6a"
15 TUNE_FEATURES:tune-armv8-6a-crypto = "${TUNE_FEATURES:tune-armv8-6a} crypto"
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H A Darch-armv8-4a.inc1 DEFAULTTUNE ?= "armv8-4a"
3 TUNEVALID[armv8-4a] = "Enable instructions for ARMv8.4-a"
4 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8-4a', ' -march=armv8.4-a', '', d)…
6 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8-4a', 'armv8-4a:', '', d)}"
12 AVAILTUNES += "armv8-4a armv8-4a-crypto armv8-4a-crypto-sve"
13 ARMPKGARCH:tune-armv8-4a ?= "armv8-4a"
14 ARMPKGARCH:tune-armv8-4a-crypto ?= "armv8-4a"
15 ARMPKGARCH:tune-armv8-4a-crypto-sve ?= "armv8-4a"
16 TUNE_FEATURES:tune-armv8-4a = "aarch64 armv8-4a"
17 TUNE_FEATURES:tune-armv8-4a-crypto = "${TUNE_FEATURES:tune-armv8-4a} crypto"
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H A Darch-armv8-5a.inc1 DEFAULTTUNE ?= "armv8-5a"
3 TUNEVALID[armv8-5a] = "Enable instructions for ARMv8.5-a"
4 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8-5a', ' -march=armv8.5-a', '', d)…
6 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8-5a', 'armv8-5a:', '', d)}"
12 AVAILTUNES += "armv8-5a armv8-5a-crypto armv8-5a-crypto-sve"
13 ARMPKGARCH:tune-armv8-5a ?= "armv8-5a"
14 ARMPKGARCH:tune-armv8-5a-crypto ?= "armv8-5a"
15 ARMPKGARCH:tune-armv8-5a-crypto-sve ?= "armv8-5a"
16 TUNE_FEATURES:tune-armv8-5a = "aarch64 armv8-5a"
17 TUNE_FEATURES:tune-armv8-5a-crypto = "${TUNE_FEATURES:tune-armv8-5a} crypto"
[all …]
/openbmc/linux/lib/math/
H A Dgcd.c23 unsigned long gcd(unsigned long a, unsigned long b) in gcd() argument
25 unsigned long r = a | b; in gcd()
27 if (!a || !b) in gcd()
35 a >>= __ffs(a); in gcd()
36 if (a == 1) in gcd()
38 if (a == b) in gcd()
39 return a << __ffs(r); in gcd()
41 if (a < b) in gcd()
42 swap(a, b); in gcd()
43 a -= b; in gcd()
[all …]
/openbmc/qemu/target/alpha/
H A Dvax_helper.c33 CPU_FloatU a; in float32_to_f() local
35 a.f = fa; in float32_to_f()
36 sig = ((uint64_t)a.l & 0x80000000) << 32; in float32_to_f()
37 exp = (a.l >> 23) & 0xff; in float32_to_f()
38 mant = ((uint64_t)a.l & 0x007fffff) << 29; in float32_to_f()
63 static float32 f_to_float32(CPUAlphaState *env, uintptr_t retaddr, uint64_t a) in f_to_float32() argument
68 exp = ((a >> 55) & 0x80) | ((a >> 52) & 0x7f); in f_to_float32()
69 mant_sig = ((a >> 32) & 0x80000000) | ((a >> 29) & 0x007fffff); in f_to_float32()
86 uint32_t helper_f_to_memory(uint64_t a) in helper_f_to_memory() argument
89 r = (a & 0x00001fffe0000000ull) >> 13; in helper_f_to_memory()
[all …]
/openbmc/linux/arch/alpha/include/asm/
H A Dio_trivial.h10 IO_CONCAT(__IO_PREFIX,ioread8)(const void __iomem *a) in IO_CONCAT()
12 return __kernel_ldbu(*(const volatile u8 __force *)a); in IO_CONCAT()
16 IO_CONCAT(__IO_PREFIX,ioread16)(const void __iomem *a) in IO_CONCAT()
18 return __kernel_ldwu(*(const volatile u16 __force *)a); in IO_CONCAT()
22 IO_CONCAT(__IO_PREFIX,iowrite8)(u8 b, void __iomem *a) in IO_CONCAT()
24 __kernel_stb(b, *(volatile u8 __force *)a); in IO_CONCAT()
28 IO_CONCAT(__IO_PREFIX,iowrite16)(u16 b, void __iomem *a) in IO_CONCAT()
30 __kernel_stw(b, *(volatile u16 __force *)a); in IO_CONCAT()
36 IO_CONCAT(__IO_PREFIX,ioread32)(const void __iomem *a) in IO_CONCAT()
38 return *(const volatile u32 __force *)a; in IO_CONCAT()
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/openbmc/linux/arch/sh/include/asm/
H A Daddrspace.h24 #define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) argument
30 #define P1SEGADDR(a) \ argument
31 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
32 #define P2SEGADDR(a) \ argument
33 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
34 #define P3SEGADDR(a) \ argument
35 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
36 #define P4SEGADDR(a) \ argument
37 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
42 #define P1SEGADDR(a) ({ (void)(a); BUG(); NULL; }) argument
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-sme.c121 static bool trans_ZERO(DisasContext *s, arg_ZERO *a) in trans_ZERO() argument
127 gen_helper_sme_zero(tcg_env, tcg_constant_i32(a->imm), in trans_ZERO()
133 static bool trans_MOVA(DisasContext *s, arg_MOVA *a) in trans_MOVA() argument
162 t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); in trans_MOVA()
163 t_zr = vec_full_reg_ptr(s, a->zr); in trans_MOVA()
164 t_pg = pred_full_reg_ptr(s, a->pg); in trans_MOVA()
169 if (a->v) { in trans_MOVA()
171 if (a->to_vec) { in trans_MOVA()
172 zc_fns[a->esz](t_zr, t_za, t_pg, t_desc); in trans_MOVA()
174 cz_fns[a->esz](t_za, t_zr, t_pg, t_desc); in trans_MOVA()
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H A Dtranslate-a64.c1324 static bool do_gvec_op2_ool(DisasContext *s, arg_qrr_e *a, int data, in do_gvec_op2_ool() argument
1327 if (!a->q && a->esz == MO_64) { in do_gvec_op2_ool()
1331 gen_gvec_op2_ool(s, a->q, a->rd, a->rn, data, fn); in do_gvec_op2_ool()
1336 static bool do_gvec_op3_ool(DisasContext *s, arg_qrrr_e *a, int data, in do_gvec_op3_ool() argument
1339 if (!a->q && a->esz == MO_64) { in do_gvec_op3_ool()
1343 gen_gvec_op3_ool(s, a->q, a->rd, a->rn, a->rm, data, fn); in do_gvec_op3_ool()
1348 static bool do_gvec_fn3(DisasContext *s, arg_qrrr_e *a, GVecGen3Fn *fn) in do_gvec_fn3() argument
1350 if (!a->q && a->esz == MO_64) { in do_gvec_fn3()
1354 gen_gvec_fn3(s, a->q, a->rd, a->rn, a->rm, fn, a->esz); in do_gvec_fn3()
1359 static bool do_gvec_fn3_no64(DisasContext *s, arg_qrrr_e *a, GVecGen3Fn *fn) in do_gvec_fn3_no64() argument
[all …]
H A Dtranslate.c408 static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) in gen_smul_dual() argument
412 tcg_gen_ext16s_i32(tmp1, a); in gen_smul_dual()
415 tcg_gen_sari_i32(a, a, 16); in gen_smul_dual()
417 tcg_gen_mul_i32(b, b, a); in gen_smul_dual()
418 tcg_gen_mov_i32(a, tmp1); in gen_smul_dual()
3597 static bool trans_MCR(DisasContext *s, arg_MCR *a) in trans_MCR() argument
3599 if (!valid_cp(s, a->cp)) { in trans_MCR()
3602 do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, in trans_MCR()
3603 false, a->rt, 0); in trans_MCR()
3607 static bool trans_MRC(DisasContext *s, arg_MRC *a) in trans_MRC() argument
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Dio.h42 #define __arch_getb(a) (*(volatile unsigned char *)(a)) argument
43 #define __arch_getw(a) (*(volatile unsigned short *)(a)) argument
44 #define __arch_getl(a) (*(volatile unsigned int *)(a)) argument
45 #define __arch_getq(a) (*(volatile unsigned long long *)(a)) argument
47 #define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) argument
48 #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) argument
49 #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) argument
50 #define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v)) argument
97 #define __raw_writeb(v,a) __arch_putb(v,a) argument
98 #define __raw_writew(v,a) __arch_putw(v,a) argument
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Daddrspace.h48 #define KSEGX(a) ((_ACAST32_(a)) & _ACAST32_(0xe0000000)) argument
53 #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) argument
54 #define XPHYSADDR(a) ((_ACAST64_(a)) & \ argument
73 #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) argument
74 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) argument
75 #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) argument
76 #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) argument
80 #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) argument
81 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) argument
82 #define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) argument
[all …]
/openbmc/linux/tools/testing/selftests/bpf/progs/
H A Dtest_jhash.h12 #define __jhash_mix(a, b, c) \ argument
14 a -= c; a ^= rol32(c, 4); c += b; \
15 b -= a; b ^= rol32(a, 6); a += c; \
16 c -= b; c ^= rol32(b, 8); b += a; \
17 a -= c; a ^= rol32(c, 16); c += b; \
18 b -= a; b ^= rol32(a, 19); a += c; \
19 c -= b; c ^= rol32(b, 4); b += a; \
22 #define __jhash_final(a, b, c) \ argument
25 a ^= c; a -= rol32(c, 11); \
26 b ^= a; b -= rol32(a, 25); \
[all …]
/openbmc/linux/fs/smb/common/
H A Dcifs_md4.c50 #define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s)) argument
51 #define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (u32)0x5A827999,s)) argument
52 #define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (u32)0x6ED9EBA1,s)) argument
56 u32 a, b, c, d; in md4_transform() local
58 a = hash[0]; in md4_transform()
63 ROUND1(a, b, c, d, in[0], 3); in md4_transform()
64 ROUND1(d, a, b, c, in[1], 7); in md4_transform()
65 ROUND1(c, d, a, b, in[2], 11); in md4_transform()
66 ROUND1(b, c, d, a, in[3], 19); in md4_transform()
67 ROUND1(a, b, c, d, in[4], 3); in md4_transform()
[all …]
/openbmc/qemu/tests/tcg/multiarch/
H A Dsha1.c74 uint32_t a, b, c, d, e; in SHA1Transform() local
91 a = state[0]; in SHA1Transform()
97 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); in SHA1Transform()
98 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); in SHA1Transform()
99 R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); in SHA1Transform()
100 R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); in SHA1Transform()
101 R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); in SHA1Transform()
102 R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); in SHA1Transform()
103 R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); in SHA1Transform()
104 R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); in SHA1Transform()
[all …]

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