/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
H A D | dce110_clk_mgr.c | 101 uint32_t vertical_total_min = stream->timing.v_total; in dce110_get_min_vblank_time_us() 106 vertical_blank_in_pixels = stream->timing.h_total * in dce110_get_min_vblank_time_us() 108 - stream->timing.v_addressable); in dce110_get_min_vblank_time_us() 110 * 10000 / stream->timing.pix_clk_100hz; in dce110_get_min_vblank_time_us() 163 cfg->v_refresh = stream->timing.pix_clk_100hz * 100; in dce110_fill_display_configs() 164 cfg->v_refresh /= stream->timing.h_total; in dce110_fill_display_configs() 165 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) in dce110_fill_display_configs() 166 / stream->timing.v_total; in dce110_fill_display_configs() 237 const struct dc_crtc_timing *timing = in dce11_pplib_apply_display_requirements() local 238 &context->streams[0]->timing; in dce11_pplib_apply_display_requirements() [all …]
|
/openbmc/linux/drivers/media/test-drivers/vidtv/ |
H A D | vidtv_mux.c | 120 m->timing.past_jiffies = m->timing.current_jiffies; in vidtv_mux_update_clk() 121 m->timing.current_jiffies = get_jiffies_64(); in vidtv_mux_update_clk() 124 m->timing.past_jiffies); in vidtv_mux_update_clk() 234 args.pcr = m->timing.clk; in vidtv_mux_push_pcr() 251 next_pcr_at = m->timing.start_jiffies + in vidtv_mux_should_push_pcr() 253 m->timing.pcr_period_usecs); in vidtv_mux_should_push_pcr() 265 next_si_at = m->timing.start_jiffies + in vidtv_mux_should_push_si() 267 m->timing.si_period_usecs); in vidtv_mux_should_push_si() 305 args.pcr = m->timing.clk; in vidtv_mux_packetize_access_units() 465 m->timing.start_jiffies = get_jiffies_64(); in vidtv_mux_start_thread() [all …]
|
/openbmc/linux/drivers/mmc/host/ |
H A D | dw_mmc-exynos.c | 257 if (timing == MMC_TIMING_MMC_HS400) in dw_mci_exynos_config_hs400() 266 if (timing == MMC_TIMING_MMC_HS400) { in dw_mci_exynos_config_hs400() 315 u32 timing = ios->timing, clksel; in dw_mci_exynos_set_ios() local 317 switch (timing) { in dw_mci_exynos_set_ios() 347 dw_mci_exynos_config_hs400(host, timing); in dw_mci_exynos_set_ios() 357 u32 timing[2]; in dw_mci_exynos_parse_dt() local 381 "samsung,dw-mshc-sdr-timing", timing, 2); in dw_mci_exynos_parse_dt() 385 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); in dw_mci_exynos_parse_dt() 388 "samsung,dw-mshc-ddr-timing", timing, 2); in dw_mci_exynos_parse_dt() 392 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); in dw_mci_exynos_parse_dt() [all …]
|
H A D | sdhci_am654.c | 256 unsigned char timing) in sdhci_am654_setup_delay_chain() argument 267 sdhci_am654->itap_del_ena[timing]); in sdhci_am654_setup_delay_chain() 274 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_set_clock() local 290 if (timing == MMC_TIMING_MMC_HS400) { in sdhci_am654_set_clock() 305 if (timing == MMC_TIMING_MMC_HS400) { in sdhci_am654_set_clock() 307 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1]; in sdhci_am654_set_clock() 326 unsigned char timing = host->mmc->ios.timing; in sdhci_j721e_4bit_set_clock() local 367 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_write_b() local 372 switch (timing) { in sdhci_am654_write_b() 502 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_platform_execute_tuning() local [all …]
|
H A D | dw_mmc-hi3798cv200.c | 32 if (ios->timing == MMC_TIMING_MMC_DDR52 || in dw_mci_hi3798cv200_set_ios() 33 ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798cv200_set_ios() 40 if (ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_hi3798cv200_set_ios() 47 if (ios->timing == MMC_TIMING_MMC_HS400) in dw_mci_hi3798cv200_set_ios() 53 if (ios->timing == MMC_TIMING_MMC_HS || in dw_mci_hi3798cv200_set_ios() 54 ios->timing == MMC_TIMING_LEGACY) in dw_mci_hi3798cv200_set_ios() 56 else if (ios->timing == MMC_TIMING_MMC_HS200) in dw_mci_hi3798cv200_set_ios()
|
H A D | sdhci-brcmstb.c | 99 unsigned int timing) in sdhci_brcmstb_set_uhs_signaling() argument 104 __func__, timing); in sdhci_brcmstb_set_uhs_signaling() 108 if ((timing == MMC_TIMING_MMC_HS200) || in sdhci_brcmstb_set_uhs_signaling() 109 (timing == MMC_TIMING_UHS_SDR104)) in sdhci_brcmstb_set_uhs_signaling() 111 else if (timing == MMC_TIMING_UHS_SDR12) in sdhci_brcmstb_set_uhs_signaling() 113 else if (timing == MMC_TIMING_SD_HS || in sdhci_brcmstb_set_uhs_signaling() 114 timing == MMC_TIMING_MMC_HS || in sdhci_brcmstb_set_uhs_signaling() 115 timing == MMC_TIMING_UHS_SDR25) in sdhci_brcmstb_set_uhs_signaling() 117 else if (timing == MMC_TIMING_UHS_SDR50) in sdhci_brcmstb_set_uhs_signaling() 120 (timing == MMC_TIMING_MMC_DDR52)) in sdhci_brcmstb_set_uhs_signaling() [all …]
|
/openbmc/linux/drivers/nvmem/ |
H A D | vf610-ocotp.c | 94 int timing; member 118 u32 timing; in vf610_ocotp_calculate_timing() local 127 timing = BF(relax, OCOTP_TIMING_RELAX); in vf610_ocotp_calculate_timing() 128 timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ); in vf610_ocotp_calculate_timing() 129 timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG); in vf610_ocotp_calculate_timing() 131 return timing; in vf610_ocotp_calculate_timing() 158 writel(ocotp->timing, base + OCOTP_TIMING); in vf610_ocotp_read() 233 ocotp_dev->timing = vf610_ocotp_calculate_timing(ocotp_dev); in vf610_ocotp_probe()
|
/openbmc/u-boot/include/ |
H A D | display.h | 32 int display_read_timing(struct udevice *dev, struct display_timing *timing); 43 const struct display_timing *timing); 61 int (*read_timing)(struct udevice *dev, struct display_timing *timing); 82 const struct display_timing *timing);
|
/openbmc/linux/Documentation/driver-api/memory-devices/ |
H A D | ti-gpmc.rst | 20 GPMC generic timing calculation: 29 generic timing routine was developed to achieve above requirements. 37 happen that timing as specified by peripheral datasheet is not present 38 in timing structure, in this scenario, try to correlate peripheral 39 timing to the one available. If that doesn't work, try to add a new 40 field as required by peripheral, educate generic timing routine to 45 Generic timing routine has been verified to work properly on 48 A word of caution: generic timing routine has been developed based 50 custom timing routines, a kind of reverse engineering without 52 in mainline having custom timing routine) and by simulation. [all …]
|
/openbmc/linux/drivers/mmc/core/ |
H A D | host.h | 68 return card->host->ios.timing == MMC_TIMING_MMC_HS200; in mmc_card_hs200() 73 return card->host->ios.timing == MMC_TIMING_MMC_DDR52; in mmc_card_ddr52() 78 return card->host->ios.timing == MMC_TIMING_MMC_HS400; in mmc_card_hs400() 88 return host->ios.timing == MMC_TIMING_SD_EXP || in mmc_card_sd_express() 89 host->ios.timing == MMC_TIMING_SD_EXP_1_2V; in mmc_card_sd_express()
|
/openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_dsc.h | 75 const struct dc_crtc_timing *timing, 84 const struct dc_crtc_timing *timing, 88 uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing, 92 const struct dc_crtc_timing *timing, 101 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
|
/openbmc/u-boot/drivers/video/sunxi/ |
H A D | sunxi_lcd.c | 21 struct display_timing timing; member 69 struct display_timing *timing) in sunxi_lcd_read_timing() argument 73 memcpy(timing, &priv->timing, sizeof(struct display_timing)); in sunxi_lcd_read_timing() 100 &priv->timing, &channel_bpp); in sunxi_lcd_probe() 118 0, &priv->timing)) { in sunxi_lcd_probe()
|
/openbmc/u-boot/board/samsung/common/ |
H A D | board.c | 190 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, in decode_sromc() 236 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | in board_eth_init() 237 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | in board_eth_init() 238 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | in board_eth_init() 239 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | in board_eth_init() 240 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | in board_eth_init() 241 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | in board_eth_init() 242 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); in board_eth_init()
|
/openbmc/linux/Documentation/devicetree/bindings/mmc/ |
H A D | sdhci-sprd.txt | 33 - sprd,phy-delay-legacy: Delay value for legacy timing. 34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing. 35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing. 36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing. 37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing. 38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing. 39 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing. 40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing. 41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
|
H A D | samsung,exynos-dw-mshc.yaml | 51 samsung,dw-mshc-ddr-timing: 63 See also samsung,dw-mshc-hs400-timing property. 65 samsung,dw-mshc-hs400-timing: 77 Valid values for SDR and DDR CIU clock timing:: 83 If missing, values from samsung,dw-mshc-ddr-timing property are used. 85 samsung,dw-mshc-sdr-timing: 97 See also samsung,dw-mshc-hs400-timing property. 111 - samsung,dw-mshc-ddr-timing 112 - samsung,dw-mshc-sdr-timing 148 samsung,dw-mshc-sdr-timing = <0 4>; [all …]
|
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_opp.c | 312 const struct dc_crtc_timing *timing) in opp1_program_stereo() argument 316 uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; in opp1_program_stereo() 317 uint32_t space1_size = timing->v_total - timing->v_addressable; in opp1_program_stereo() 319 uint32_t space2_size = timing->v_total - timing->v_addressable; in opp1_program_stereo() 337 if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE) in opp1_program_stereo()
|
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
H A D | ramgt215.c | 379 timing[2] = (T(CWL) - 1) << 24 | in gt215_ram_timing_calc() 383 timing[3] = (cur3 & 0x00ff0000) | in gt215_ram_timing_calc() 387 timing[4] = T(20) << 24 | in gt215_ram_timing_calc() 391 timing[5] = T(RFC) << 24 | in gt215_ram_timing_calc() 395 timing[6] = (0x5a + T(CL)) << 16 | in gt215_ram_timing_calc() 398 timing[7] = (cur7 & 0xff000000) | in gt215_ram_timing_calc() 401 timing[8] = cur8 & 0xffffff00; in gt215_ram_timing_calc() 408 timing[8] |= T(CL); in gt215_ram_timing_calc() 415 timing[0], timing[1], timing[2], timing[3]); in gt215_ram_timing_calc() 417 timing[4], timing[5], timing[6], timing[7]); in gt215_ram_timing_calc() [all …]
|
/openbmc/linux/drivers/gpu/drm/msm/dsi/phy/ |
H A D | dsi_phy.h | 110 struct msm_dsi_dphy_timing timing; member 129 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, 131 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, 133 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 135 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 137 int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
|
H A D | dsi_phy_28nm_8960.c | 476 struct msm_dsi_dphy_timing *timing) in dsi_28nm_dphy_set_timing() argument 481 DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_dphy_set_timing() 488 DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_28nm_dphy_set_timing() 490 DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_28nm_dphy_set_timing() 496 DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_28nm_dphy_set_timing() 498 DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | in dsi_28nm_dphy_set_timing() 499 DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); in dsi_28nm_dphy_set_timing() 501 DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); in dsi_28nm_dphy_set_timing() 587 struct msm_dsi_dphy_timing *timing = &phy->timing; in dsi_28nm_phy_enable() local 592 if (msm_dsi_dphy_timing_calc(timing, clk_req)) { in dsi_28nm_phy_enable() [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/mips/cavium/ |
H A D | bootbus.txt | 32 - cavium,t-adr: A cell specifying the ADR timing (in nS). 34 - cavium,t-ce: A cell specifying the CE timing (in nS). 36 - cavium,t-oe: A cell specifying the OE timing (in nS). 38 - cavium,t-we: A cell specifying the WE timing (in nS). 40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). 42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). 44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS). 46 - cavium,t-wait: A cell specifying the WAIT timing (in nS). 48 - cavium,t-page: A cell specifying the PAGE timing (in nS). 50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
|
/openbmc/u-boot/drivers/video/tegra124/ |
H A D | dp.c | 482 const struct display_timing *timing, in tegra_dc_dp_calc_config() argument 516 timing->pixelclock.typ)); in tegra_dc_dp_calc_config() 620 timing->hfront_porch.typ + timing->hsync_len.typ - 7) * in tegra_dc_dp_calc_config() 621 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config() 652 const struct display_timing *timing, in tegra_dc_dp_init_max_link_cfg() argument 1306 const struct display_timing *timing, in tegra_dp_do_link_training() argument 1351 const struct display_timing *timing) in tegra_dc_dp_explore_link_cfg() argument 1355 if (!timing->pixelclock.typ || !timing->hactive.typ || in tegra_dc_dp_explore_link_cfg() 1356 !timing->vactive.typ) { in tegra_dc_dp_explore_link_cfg() 1424 const struct display_timing *timing) in tegra_dc_dp_check_sink() argument [all …]
|
/openbmc/linux/sound/pci/ |
H A D | sis7019.c | 82 struct voice *timing; member 331 if (!voice->timing) in sis_interrupt() 393 if (voice->timing) { in sis_free_voice() 397 voice->timing = NULL; in sis_free_voice() 456 if (voice->timing) in sis_alloc_timing_voice() 459 if (!voice->timing) in sis_alloc_timing_voice() 464 voice->timing = NULL; in sis_alloc_timing_voice() 606 voice = voice->timing; in sis_pcm_trigger() 702 struct voice *timing = voice->timing; in sis_prepare_timing_voice() local 762 timing->sso = sso; in sis_prepare_timing_voice() [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/media/xilinx/ |
H A D | xlnx,v-tc.txt | 4 The Video Timing Controller is a general purpose video timing generator and 13 - clocks: Must contain a clock specifier for the VTC core and timing 18 - xlnx,detector: The VTC has a timing detector 19 - xlnx,generator: The VTC has a timing generator
|
/openbmc/linux/drivers/gpu/drm/meson/ |
H A D | meson_dw_mipi_dsi.c | 180 struct dw_mipi_dsi_dphy_timing *timing) in dw_mipi_dsi_phy_get_timing() argument 189 timing->clk_lp2hs = 23; in dw_mipi_dsi_phy_get_timing() 190 timing->clk_hs2lp = 38; in dw_mipi_dsi_phy_get_timing() 191 timing->data_lp2hs = 15; in dw_mipi_dsi_phy_get_timing() 192 timing->data_hs2lp = 9; in dw_mipi_dsi_phy_get_timing() 196 timing->clk_lp2hs = 37; in dw_mipi_dsi_phy_get_timing() 197 timing->clk_hs2lp = 135; in dw_mipi_dsi_phy_get_timing() 198 timing->data_lp2hs = 50; in dw_mipi_dsi_phy_get_timing() 199 timing->data_hs2lp = 3; in dw_mipi_dsi_phy_get_timing()
|
/openbmc/linux/drivers/mtd/nand/raw/ |
H A D | cafe_nand.c | 92 static int timing[3]; variable 728 timing[0], timing[1], timing[2]); in cafe_nand_probe() 734 if (timing[0] | timing[1] | timing[2]) { in cafe_nand_probe() 736 timing[0], timing[1], timing[2]); in cafe_nand_probe() 739 timing[0] = timing[1] = timing[2] = 0xffffffff; in cafe_nand_probe() 747 cafe_writel(cafe, timing[0], NAND_TIMING1); in cafe_nand_probe() 748 cafe_writel(cafe, timing[1], NAND_TIMING2); in cafe_nand_probe() 749 cafe_writel(cafe, timing[2], NAND_TIMING3); in cafe_nand_probe() 853 cafe_writel(cafe, timing[0], NAND_TIMING1); in cafe_nand_resume() 854 cafe_writel(cafe, timing[1], NAND_TIMING2); in cafe_nand_resume() [all …]
|