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/openbmc/qemu/hw/timer/
H A Dimx_epit.c70 if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { in imx_epit_update_int()
94 s->cr = 0; in imx_epit_reset()
98 s->sr = 0; in imx_epit_reset()
100 s->cmp = 0; in imx_epit_reset()
168 bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s); in imx_epit_update_compare_timer()
296 s->lr = value; in imx_epit_write_lr()
303 ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); in imx_epit_write_lr()
304 ptimer_set_limit(s->timer_cmp, s->lr, 0); in imx_epit_write_lr()
307 ptimer_set_count(s->timer_reload, s->lr); in imx_epit_write_lr()
318 s->cmp = value; in imx_epit_write_cmp()
[all …]
H A Dstm32f2xx_timer.c53 if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) { in stm32f2xx_timer_interrupt()
56 stm32f2xx_timer_set_alarm(s, s->hit_time); in stm32f2xx_timer_interrupt()
65 s->tim_ccr2 / (100 * (s->tim_psc + 1))); in stm32f2xx_timer_interrupt()
71 return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1); in stm32f2xx_ns_to_ticks()
86 ticks = s->tim_arr - (now_ticks - s->tick_offset); in stm32f2xx_timer_set_alarm()
102 s->tim_cr1 = 0; in stm32f2xx_timer_reset()
103 s->tim_cr2 = 0; in stm32f2xx_timer_reset()
106 s->tim_sr = 0; in stm32f2xx_timer_reset()
119 s->tim_or = 0; in stm32f2xx_timer_reset()
121 s->tick_offset = stm32f2xx_ns_to_ticks(s, now); in stm32f2xx_timer_reset()
[all …]
H A Dsse-timer.c124 return sse_cntpct(s) >= s->cntp_cval; in sse_timer_status()
193 s->cntp_aival = sse_cntpct(s) + s->cntp_aival_reload; in sse_autoinc()
194 sse_set_timer(s, s->cntp_aival); in sse_autoinc()
207 s->cntp_aival = count + s->cntp_aival_reload; in sse_timer_cb()
209 sse_set_timer(s, s->cntp_aival); in sse_timer_cb()
238 r = extract64(s->cntp_cval - sse_cntpct(s), 0, 32); in sse_timer_read()
292 s->cntp_cval = deposit64(s->cntp_cval, 0, 32, value); in sse_timer_write()
296 s->cntp_cval = deposit64(s->cntp_cval, 32, 32, value); in sse_timer_write()
300 s->cntp_cval = sse_cntpct(s) + sextract64(value, 0, 32); in sse_timer_write()
379 s->cntfrq = 0; in sse_timer_reset()
[all …]
/openbmc/qemu/hw/char/
H A Dcadence_uart.c131 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; in uart_update_status()
132 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; in uart_update_status()
137 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; in uart_update_status()
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
181 baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); in uart_parameters_setup()
291 s->rx_fifo[s->rx_wpos] = buf[i]; in uart_write_rx_fifo()
317 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); in cadence_uart_xmit()
321 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); in cadence_uart_xmit()
355 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
[all …]
H A Dmcf_uart.c74 if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ) in OBJECT_DECLARE_SIMPLE_TYPE()
78 qemu_set_irq(s->irq, (s->isr & s->imr) != 0); in OBJECT_DECLARE_SIMPLE_TYPE()
87 return s->mr[s->current_mr]; in mcf_uart_read()
101 s->fifo[i] = s->fifo[i + 1]; in mcf_uart_read()
126 if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) { in mcf_uart_do_tx()
207 s->mr[s->current_mr] = val; in mcf_uart_write()
238 s->mr[0] = 0; in mcf_uart_reset()
243 s->isr = 0; in mcf_uart_reset()
244 s->imr = 0; in mcf_uart_reset()
253 s->fifo[s->fifo_len] = data; in mcf_uart_push_byte()
[all …]
H A Dnrf51_uart.c46 if (!s->enabled) { in uart_read()
52 r = s->rx_fifo[s->rx_fifo_pos]; in uart_read()
53 if (s->rx_started && s->rx_fifo_len) { in uart_read()
54 s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH; in uart_read()
84 s->watch_tag = 0; in uart_transmit()
88 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, in uart_transmit()
107 if (s->watch_tag) { in uart_cancel_transmit()
126 if (!s->pending_tx_byte && s->tx_started) { in uart_write()
207 memset(s->reg, 0, sizeof(s->reg)); in nrf51_uart_reset()
246 return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0; in uart_can_receive()
[all …]
H A Dibex_uart.c130 s->rx_level += 1; in ibex_uart_receive()
149 s->tx_level = 0; in ibex_uart_xmit()
153 if (!s->tx_level) { in ibex_uart_xmit()
162 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); in ibex_uart_xmit()
166 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level); in ibex_uart_xmit()
169 if (s->tx_level) { in ibex_uart_xmit()
210 memcpy(s->tx_fifo + s->tx_level, buf, size); in uart_write_tx_fifo()
246 s->tx_level = 0; in ibex_uart_reset()
247 s->rx_level = 0; in ibex_uart_reset()
292 if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) { in ibex_uart_read()
[all …]
/openbmc/qemu/hw/usb/
H A Dtusb6010.c250 qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); in tusb_intr_update()
252 qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); in tusb_intr_update()
258 if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) in tusb_usbip_intr_update()
264 if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask) in tusb_usbip_intr_update()
276 if (s->dma_intr & ~s->dma_mask) in tusb_dma_intr_update()
700 if (s->power) { in tusb_power_tick()
743 s->usbip_intr = musb_core_intr_get(s->musb); in tusb_musb_core_intr()
787 s->power = 0; in tusb6010_reset()
806 s->pullup[0] = s->pullup[1] = 0; in tusb6010_reset()
809 s->rx_config[i] = s->tx_config[i] = 0; in tusb6010_reset()
[all …]
/openbmc/qemu/hw/sd/
H A Dssi-sd.c179 } else if (s->cmd == 8 || s->cmd == 58) { in OBJECT_DECLARE_SIMPLE_TYPE()
196 s->arglen = (s->cmd == 13) ? 2 : 1; in OBJECT_DECLARE_SIMPLE_TYPE()
199 if (s->cmd == 28 || s->cmd == 29 || s->cmd == 38) { in OBJECT_DECLARE_SIMPLE_TYPE()
244 s->cmdarg[s->arglen++] = val; in OBJECT_DECLARE_SIMPLE_TYPE()
252 if (s->response_pos < s->arglen) { in OBJECT_DECLARE_SIMPLE_TYPE()
254 return s->response[s->response_pos++]; in OBJECT_DECLARE_SIMPLE_TYPE()
336 (s->arglen < 0 || s->arglen >= ARRAY_SIZE(s->cmdarg))) { in ssi_sd_post_load()
340 (s->response_pos < 0 || s->response_pos >= ARRAY_SIZE(s->response) || in ssi_sd_post_load()
341 (!s->stopping && s->arglen > ARRAY_SIZE(s->response)))) { in ssi_sd_post_load()
382 memset(s->cmdarg, 0, sizeof(s->cmdarg)); in ssi_sd_reset()
[all …]
/openbmc/qemu/hw/input/
H A Dlm832x.c90 qemu_set_irq(s->nirq, !s->status); in lm_kbd_irq_update()
220 s->kbd.start &= sizeof(s->kbd.fifo) - 1; in lm_kbd_read()
223 return s->kbd.fifo[s->kbd.start]; in lm_kbd_read()
228 return s->kbd.fifo[(s->kbd.start + byte) & (sizeof(s->kbd.fifo) - 1)]; in lm_kbd_read()
261 qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 0) & 1]); in lm_kbd_write()
263 qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 2) & 1]); in lm_kbd_write()
353 s->pwm.file[s->pwm.faddr] = 0; in lm_kbd_write()
413 return lm_kbd_read(s, s->reg, s->i2c_cycle ++); in lm_i2c_rx()
423 lm_kbd_write(s, s->reg, s->i2c_cycle - 1, data); in lm_i2c_tx()
490 if (s->kbd.len >= sizeof(s->kbd.fifo)) { in lm832x_key_event()
[all …]
H A Dpckbd.c230 if (s->throttle_timer && timer_pending(s->throttle_timer)) { in kbd_safe_update_irq()
339 kbd_queue(s, s->mode, 0); in kbd_write_command()
376 kbd_queue(s, s->outport, 0); in kbd_write_command()
411 s->obdata = ps2_read_data(PS2_DEVICE(&s->ps2kbd)); in kbd_read_data()
413 s->obdata = ps2_read_data(PS2_DEVICE(&s->ps2mouse)); in kbd_read_data()
415 s->obdata = kbd_dequeue(s); in kbd_read_data()
504 return s->outport != kbd_outport_default(s); in kbd_outport_needed()
569 s->pending_tmp = s->pending; in kbd_pre_save()
595 s->outport = kbd_outport_default(s); in kbd_post_load()
597 s->pending = s->pending_tmp; in kbd_post_load()
[all …]
/openbmc/qemu/hw/misc/
H A Dmos6522.c56 if (s->ifr & s->ier) { in mos6522_update_irq()
376 if (s->ifr & s->ier) { in mos6522_read()
404 s->b = (s->b & ~s->dirb) | (val & s->dirb); in mos6522_write()
417 s->a = (s->a & ~s->dira) | (val & s->dira); in mos6522_write()
434 mos6522_timer1_update(s, &s->timers[0], in mos6522_write()
440 set_counter(s, &s->timers[0], s->timers[0].latch); in mos6522_write()
444 mos6522_timer1_update(s, &s->timers[0], in mos6522_write()
462 set_counter(s, &s->timers[1], s->timers[1].latch); in mos6522_write()
660 s->timers[0].frequency = s->frequency; in mos6522_reset_hold()
662 set_counter(s, &s->timers[0], 0xffff); in mos6522_reset_hold()
[all …]
H A Daxp2xx.c69 s->ptr = 0; in axp209_reset_enter()
70 s->count = 0; in axp209_reset_enter()
75 s->regs[0x30] = 0x60; in axp209_reset_enter()
76 s->regs[0x32] = 0x46; in axp209_reset_enter()
112 s->ptr = 0; in axp221_reset_enter()
113 s->count = 0; in axp221_reset_enter()
176 s->count = 0; in axp2xx_event()
188 ret = s->regs[s->ptr++]; in axp2xx_rx()
206 s->ptr = data; in axp2xx_tx()
207 s->count++; in axp2xx_tx()
[all …]
H A Dmchp_pfsoc_ioscb.c215 memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
219 memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
223 memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s, in mchp_pfsoc_ioscb_realize()
227 memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
231 memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
235 memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
239 memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
243 memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s, in mchp_pfsoc_ioscb_realize()
247 memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
251 memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s, in mchp_pfsoc_ioscb_realize()
[all …]
/openbmc/qemu/hw/display/
H A Dati_2d.c58 s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width); in ati_2d_blt()
60 s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height); in ati_2d_blt()
78 uint8_t *end = s->vga.vram_ptr + s->vga.vram_size; in ati_2d_blt()
86 s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, in ati_2d_blt()
87 s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, in ati_2d_blt()
88 s->regs.src_x, s->regs.src_y, dst_x, dst_y, in ati_2d_blt()
89 s->regs.dst_width, s->regs.dst_height, in ati_2d_blt()
97 s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width); in ati_2d_blt()
99 s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height); in ati_2d_blt()
125 s->regs.dst_width, s->regs.dst_height); in ati_2d_blt()
[all …]
/openbmc/linux/drivers/media/usb/airspy/
H A Dairspy.c251 s->sample_measured = s->sample; in airspy_convert_stream()
355 s->buf_list[s->buf_num], in airspy_free_stream_bufs()
356 s->dma_addr[s->buf_num]); in airspy_free_stream_bufs()
372 for (s->buf_num = 0; s->buf_num < MAX_BULK_BUFS; s->buf_num++) { in airspy_alloc_stream_bufs()
373 s->buf_list[s->buf_num] = usb_alloc_coherent(s->udev, in airspy_alloc_stream_bufs()
375 &s->dma_addr[s->buf_num]); in airspy_alloc_stream_bufs()
376 if (!s->buf_list[s->buf_num]) { in airspy_alloc_stream_bufs()
383 s->buf_list[s->buf_num], in airspy_alloc_stream_bufs()
1014 s->vb_queue.drv_priv = s; in airspy_probe()
1027 s->vdev.queue = &s->vb_queue; in airspy_probe()
[all …]
/openbmc/linux/lib/xz/
H A Dxz_dec_lzma2.c724 if (!rc_bit(&s->rc, &s->lzma.is_rep0[s->lzma.state])) { in lzma_rep_match()
732 if (!rc_bit(&s->rc, &s->lzma.is_rep1[s->lzma.state])) { in lzma_rep_match()
735 if (!rc_bit(&s->rc, &s->lzma.is_rep2[s->lzma.state])) { in lzma_rep_match()
763 dict_repeat(&s->dict, &s->lzma.len, s->lzma.rep0); in lzma_main()
776 if (rc_bit(&s->rc, &s->lzma.is_rep[s->lzma.state])) in lzma_main()
907 s->rc.in = s->temp.buf; in lzma2_lzma()
910 if (!lzma_main(s) || s->rc.in_pos > s->temp.size + tmp) in lzma2_lzma()
917 memmove(s->temp.buf, s->temp.buf + s->rc.in_pos, in lzma2_lzma()
1306 s->s.dict.mode = mode; in xz_dec_microlzma_alloc()
1334 s->s.temp.size = 0; in xz_dec_microlzma_reset()
[all …]
/openbmc/qemu/hw/intc/
H A Di8259.c82 mask = s->irr & ~s->imr; in pic_get_irq()
94 if (s->special_fully_nested_mode && s->master) { in pic_get_irq()
113 trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); in pic_update_irq()
136 if (s->ltim || (s->elcr & mask)) { in pic_set_irq()
170 if (!s->ltim && !(s->elcr & (1 << irq))) { in pic_intack()
226 s->elcr = 0; in pic_reset()
267 priority = get_priority(s, s->isr); in pic_ioport_write()
306 s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2; in pic_ioport_write()
363 s->elcr = val & s->elcr_mask; in elcr_ioport_write()
396 memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s, in pic_realize()
[all …]
/openbmc/qemu/hw/net/
H A Dne2000.c129 memcpy(s->mem, &s->c.macaddr, 6); in ne2000_reset()
135 s->mem[2 * i] = s->mem[i]; in ne2000_reset()
136 s->mem[2 * i + 1] = s->mem[i]; in ne2000_reset()
143 isr = (s->isr & s->imr) & 0x7f; in ne2000_update_irq()
146 isr ? 1 : 0, s->isr, s->imr); in ne2000_update_irq()
155 if (s->stop <= s->start) { in ne2000_buffer_full()
222 next -= (s->stop - s->start); in ne2000_receive()
501 if (s->rsar == s->stop) in ne2000_dma_update()
502 s->rsar = s->start; in ne2000_dma_update()
564 ne2000_mem_writel(s, s->rsar, val); in ne2000_asic_ioport_writel()
[all …]
/openbmc/u-boot/lib/bzip2/
H A Dbzlib_compress.c89 s->zbits[s->numZ] = (UChar)(s->bsBuff >> 24); in bsFinishWrite()
152 s->unseqToSeq[i] = s->nInUse; in makeMaps_e()
305 s->nblock, s->nMTF, s->nInUse ); in sendMTFValues()
377 s->len_pack[v][0] = (s->len[1][v] << 16) | s->len[0][v]; in sendMTFValues()
378 s->len_pack[v][1] = (s->len[3][v] << 16) | s->len[2][v]; in sendMTFValues()
379 s->len_pack[v][2] = (s->len[5][v] << 16) | s->len[4][v]; in sendMTFValues()
551 if (s->inUse[i * 16 + j]) bsW(s,1,1); else bsW(s,1,0); in sendMTFValues()
649 s->combinedCRC ^= s->blockCRC; in BZ2_compressBlock()
655 s->blockNo, s->blockCRC, s->combinedCRC, s->nblock ); in BZ2_compressBlock()
660 s->zbits = (UChar*) (&((UChar*)s->arr2)[s->nblock]); in BZ2_compressBlock()
[all …]
/openbmc/qemu/hw/ssi/
H A Dmss-spi.c127 s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS]; in update_mis()
134 update_mis(s); in spi_update_irq()
144 memset(s->regs, 0, sizeof s->regs); in mss_spi_reset()
155 rxfifo_reset(s); in mss_spi_reset()
230 while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) { in spi_flush_txfifo()
240 if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) { in spi_flush_txfifo()
259 s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >> in spi_flush_txfifo()
279 if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { in spi_write()
284 if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) { in spi_write()
286 } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { in spi_write()
[all …]
H A Dpl022.c53 s->sr = 0; in pl022_update()
70 qemu_set_irq(s->irq, (s->is & s->im) != 0); in pl022_update()
86 i = (s->tx_fifo_head - s->tx_fifo_len) & 7; in pl022_xfer()
100 while (s->tx_fifo_len && s->rx_fifo_len < 8) { in pl022_xfer()
108 s->rx_fifo[o] = val & s->bitmask; in pl022_xfer()
134 val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7]; in pl022_read()
151 return s->im & s->is; in pl022_read()
184 s->tx_fifo[s->tx_fifo_head] = value & s->bitmask; in pl022_write()
239 s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) || in pl022_post_load()
241 s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) { in pl022_post_load()
[all …]
/openbmc/qemu/hw/ppc/
H A Dppc440_pcix.c159 memory_region_init_alias(mem, OBJECT(s), name, &s->busmem, in ppc440_pcix_update_pom()
276 s->sts = val; in ppc440_pcix_reg_write4()
372 val = s->sts; in ppc440_pcix_reg_read4()
408 ppc440_pcix_clear_region(&s->bm, &s->pim[i].mr); in ppc440_pcix_reset()
410 memset(s->pom, 0, sizeof(s->pom)); in ppc440_pcix_reset()
411 memset(s->pim, 0, sizeof(s->pim)); in ppc440_pcix_reset()
415 s->sts = 0; in ppc440_pcix_reset()
501 ppc440_pcix_map_irq, &s->irq, &s->busmem, &s->iomem, in ppc440_pcix_realize()
508 memory_region_add_subregion(&s->bm, 0x0, &s->busmem); in ppc440_pcix_realize()
509 address_space_init(&s->bm_as, &s->bm, "pci-bm"); in ppc440_pcix_realize()
[all …]
/openbmc/qemu/hw/audio/
H A Dcs4231a.c334 s, in cs_reset_voices()
341 k->hold_DREQ(s->isa_dma, s->dma); in cs_reset_voices()
349 k->release_DREQ(s->isa_dma, s->dma); in cs_reset_voices()
358 k->release_DREQ(s->isa_dma, s->dma); in cs_reset_voices()
579 copy = s->voice ? (s->audio_free >> (s->tab != NULL)) : dma_len; in cs_dma_read()
616 k->release_DREQ(s->isa_dma, s->dma); in cs4231a_pre_load()
664 memory_region_init_io (&s->ioports, OBJECT(s), &cs_ioport_ops, s, in cs4231a_initfn()
675 s->isa_dma = isa_bus_get_dma(bus, s->dma); in cs4231a_realizefn()
685 s->pic = isa_bus_get_irq(bus, s->irq); in cs4231a_realizefn()
687 k->register_channel(s->isa_dma, s->dma, cs_dma_read, s); in cs4231a_realizefn()
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/openbmc/qemu/net/
H A Dl2tpv3.c190 (uint32_t *) (s->header_buf + s->session_offset), in l2tpv3_form_header()
234 s->vec->iov_base = s->header_buf; in net_l2tpv3_receive_dgram_iov()
235 s->vec->iov_len = s->offset; in net_l2tpv3_receive_dgram_iov()
311 if ((!s->udp) && (!s->ipv6)) { in l2tpv3_verify_header()
354 msgvec = s->msgvec + s->queue_tail; in net_l2tpv3_process_queue()
431 msgvec = s->msgvec + s->queue_head; in net_l2tpv3_send()
597 s->rx_session = s->tx_session; in net_init_l2tpv3()
702 if ((s->ipv6) || (s->udp)) { in net_init_l2tpv3()
703 s->header_size = s->offset; in net_init_l2tpv3()
705 s->header_size = s->offset + sizeof(struct iphdr); in net_init_l2tpv3()
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