Home
last modified time | relevance | path

Searched refs:reg_base (Results 176 – 200 of 455) sorted by relevance

12345678910>>...19

/openbmc/linux/drivers/dma/idxd/
H A Dirq.c369 idxd->reg_base + IDXD_EVLSTATUS_OFFSET + sizeof(u32)); in process_evl_entries()
370 evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET); in process_evl_entries()
382 iowrite32(evl_status.bits_lower32, idxd->reg_base + IDXD_EVLSTATUS_OFFSET); in process_evl_entries()
397 cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET); in idxd_misc_thread()
401 iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET); in idxd_misc_thread()
409 idxd->sw_err.bits[i] = ioread64(idxd->reg_base + in idxd_misc_thread()
413 idxd->reg_base + IDXD_SWERR_OFFSET); in idxd_misc_thread()
487 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); in idxd_misc_thread()
/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2600.c238 u32 reg_base = (u32)info->phy_setting; in ast2600_sdramphy_init() local
249 if (addr < reg_base) { in ast2600_sdramphy_init()
275 u32 reg_base = (u32)info->phy_status; in ast2600_sdramphy_check_status() local
280 value = readl(reg_base + 0x00); in ast2600_sdramphy_check_status()
289 value = readl(reg_base + 0x30); in ast2600_sdramphy_check_status()
295 value = readl(reg_base + 0x68); in ast2600_sdramphy_check_status()
306 value = readl(reg_base + 0xC8); in ast2600_sdramphy_check_status()
315 value = readl(reg_base + 0x7c); in ast2600_sdramphy_check_status()
327 value = readl(reg_base + 0x88); in ast2600_sdramphy_check_status()
336 value = readl(reg_base + 0x90); in ast2600_sdramphy_check_status()
[all …]
/openbmc/u-boot/drivers/clk/at91/
H A Dclk-plladiv.c22 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_get_rate()
41 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_set_rate()
H A Dpmc.c41 plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev); in at91_pmc_core_probe()
116 plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev_pmc); in at91_clk_probe()
/openbmc/linux/drivers/spi/
H A Dspi-fsl-espi.c92 void __iomem *reg_base; member
118 return ioread32be(espi->reg_base + offset); in fsl_espi_read_reg()
123 return ioread16be(espi->reg_base + offset); in fsl_espi_read_reg16()
128 return ioread8(espi->reg_base + offset); in fsl_espi_read_reg8()
134 iowrite32be(val, espi->reg_base + offset); in fsl_espi_write_reg()
140 iowrite16be(val, espi->reg_base + offset); in fsl_espi_write_reg16()
146 iowrite8(val, espi->reg_base + offset); in fsl_espi_write_reg8()
704 espi->reg_base = devm_ioremap_resource(dev, mem); in fsl_espi_probe()
705 if (IS_ERR(espi->reg_base)) { in fsl_espi_probe()
706 ret = PTR_ERR(espi->reg_base); in fsl_espi_probe()
/openbmc/linux/drivers/pci/controller/
H A Dpcie-xilinx-cpm.c132 void __iomem *reg_base; member
145 return readl_relaxed(port->reg_base + reg); in pcie_read()
151 writel_relaxed(val, port->reg_base + reg); in pcie_write()
553 port->reg_base = devm_platform_ioremap_resource_byname(pdev, in xilinx_cpm_pcie_parse_dt()
555 if (IS_ERR(port->reg_base)) in xilinx_cpm_pcie_parse_dt()
556 return PTR_ERR(port->reg_base); in xilinx_cpm_pcie_parse_dt()
558 port->reg_base = port->cfg->win; in xilinx_cpm_pcie_parse_dt()
/openbmc/linux/drivers/hwtracing/intel_th/
H A Dmsu.c130 void __iomem *reg_base; member
779 iowrite32(reg, msc->reg_base + REG_MSU_MSC0BAR); in msc_configure()
786 reg = ioread32(msc->reg_base + REG_MSU_MSC0CTL); in msc_configure()
796 iowrite32(reg, msc->reg_base + REG_MSU_MSC0CTL); in msc_configure()
842 reg = ioread32(msc->reg_base + REG_MSU_MSC0CTL); in msc_disable()
844 iowrite32(reg, msc->reg_base + REG_MSU_MSC0CTL); in msc_disable()
856 ioread32(msc->reg_base + REG_MSU_MSC0NWSA)); in msc_disable()
858 reg = ioread32(msc->reg_base + REG_MSU_MSC0STS); in msc_disable()
861 reg = ioread32(msc->reg_base + REG_MSU_MSUSTS); in msc_disable()
863 iowrite32(reg, msc->reg_base + REG_MSU_MSUSTS); in msc_disable()
[all …]
/openbmc/linux/drivers/media/platform/mediatek/jpeg/
H A Dmtk_jpeg_core.c964 mtk_jpeg_enc_reset(jpeg->reg_base); in mtk_jpeg_enc_device_run()
969 mtk_jpeg_enc_start(jpeg->reg_base); in mtk_jpeg_enc_device_run()
1032 mtk_jpeg_dec_reset(jpeg->reg_base); in mtk_jpeg_dec_device_run()
1033 mtk_jpeg_dec_set_config(jpeg->reg_base, in mtk_jpeg_dec_device_run()
1038 mtk_jpeg_dec_start(jpeg->reg_base); in mtk_jpeg_dec_device_run()
1247 jpeg->variant->hw_reset(jpeg->reg_base); in mtk_jpeg_job_timeout_work()
1266 if (IS_ERR(jpeg->reg_base)) { in mtk_jpeg_single_core_init()
1267 ret = PTR_ERR(jpeg->reg_base); in mtk_jpeg_single_core_init()
1652 comp_jpeg[hw_id]->reg_base, in mtk_jpegenc_worker()
1655 comp_jpeg[hw_id]->reg_base, in mtk_jpegenc_worker()
[all …]
/openbmc/linux/drivers/media/rc/img-ir/
H A Dimg-ir-core.c96 priv->reg_base = devm_platform_ioremap_resource(pdev, 0); in img_ir_probe()
97 if (IS_ERR(priv->reg_base)) in img_ir_probe()
98 return PTR_ERR(priv->reg_base); in img_ir_probe()
/openbmc/u-boot/board/freescale/ls1012afrdm/
H A Deth.c54 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; in pfe_eth_board_init()
67 mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; in pfe_eth_board_init()
/openbmc/linux/drivers/media/platform/mediatek/vcodec/common/
H A Dmtk_vcodec_util.c24 void __iomem *mtk_vcodec_get_reg_addr(void __iomem **reg_base, unsigned int reg_idx) in mtk_vcodec_get_reg_addr() argument
30 return reg_base[reg_idx]; in mtk_vcodec_get_reg_addr()
42 writel(val, dev->reg_base[VDEC_SYS] + reg); in mtk_vcodec_write_vdecsys()
/openbmc/linux/drivers/clocksource/
H A Dtimer-loongson1-pwm.c34 void __iomem *reg_base; member
183 count = readl(ls1x_cs->reg_base + PWM_CNTR); in ls1x_clocksource_read()
228 ls1x_clocksource.reg_base = timer_of_base(to); in ls1x_pwm_clocksource_init()
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5-subcmu.c68 exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs, in exynos5_subcmus_init()
79 exynos5_subcmu_clk_save(ctx->reg_base, info->suspend_regs, in exynos5_subcmu_suspend()
92 exynos5_subcmu_clk_restore(ctx->reg_base, info->suspend_regs, in exynos5_subcmu_resume()
H A Dclk-s3c64xx.c56 static void __iomem *reg_base; variable
399 reg_base = base; in s3c64xx_clk_init()
403 reg_base = of_iomap(np, 0); in s3c64xx_clk_init()
404 if (!reg_base) in s3c64xx_clk_init()
408 ctx = samsung_clk_init(NULL, reg_base, NR_CLKS); in s3c64xx_clk_init()
453 samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs, in s3c64xx_clk_init()
456 samsung_clk_sleep_init(reg_base, s3c6410_clk_regs, in s3c64xx_clk_init()
H A Dclk-s5pv210.c80 static void __iomem *reg_base; variable
746 ctx = samsung_clk_init(NULL, reg_base, NR_CLKS); in __s5pv210_clk_init()
786 samsung_clk_sleep_init(reg_base, s5pv210_clk_regs, in __s5pv210_clk_init()
802 reg_base = of_iomap(np, 0); in s5pv210_clk_dt_init()
803 if (!reg_base) in s5pv210_clk_dt_init()
812 reg_base = of_iomap(np, 0); in s5p6442_clk_dt_init()
813 if (!reg_base) in s5p6442_clk_dt_init()
/openbmc/linux/drivers/net/can/mscan/
H A Dmpc5xxx_can.c315 priv->reg_base = base; in mpc5xxx_can_probe()
336 priv->reg_base, dev->irq, priv->can.clock.freq); in mpc5xxx_can_probe()
365 iounmap(priv->reg_base); in mpc5xxx_can_remove()
376 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; in mpc5xxx_can_suspend()
387 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; in mpc5xxx_can_resume()
/openbmc/linux/drivers/fpga/
H A Dsocfpga-a10.c472 void __iomem *reg_base; in socfpga_a10_fpga_probe() local
481 reg_base = devm_platform_ioremap_resource(pdev, 0); in socfpga_a10_fpga_probe()
482 if (IS_ERR(reg_base)) in socfpga_a10_fpga_probe()
483 return PTR_ERR(reg_base); in socfpga_a10_fpga_probe()
491 priv->regmap = devm_regmap_init_mmio(dev, reg_base, in socfpga_a10_fpga_probe()
/openbmc/linux/drivers/rtc/
H A Drtc-x1205.c89 unsigned char reg_base) in x1205_get_datetime() argument
91 unsigned char dt_addr[2] = { 0, reg_base }; in x1205_get_datetime()
123 if (reg_base < X1205_CCR_BASE) in x1205_get_datetime()
173 u8 reg_base, unsigned char alm_enable) in x1205_set_datetime() argument
176 unsigned char rdata[10] = { 0, reg_base }; in x1205_set_datetime()
209 if (reg_base < X1205_CCR_BASE) in x1205_set_datetime()
236 if (reg_base < X1205_CCR_BASE) { in x1205_set_datetime()
/openbmc/linux/drivers/net/can/sja1000/
H A Dplx_pci.c399 return ioread8(priv->reg_base + port); in plx_pci_read_reg()
404 iowrite8(val, priv->reg_base + port); in plx_pci_write_reg()
582 if (priv->reg_base) in plx_pci_del_card()
583 pci_iounmap(pdev, priv->reg_base); in plx_pci_del_card()
684 priv->reg_base = addr + cm->offset; in plx_pci_add_card()
708 "registered as %s\n", i + 1, priv->reg_base, in plx_pci_add_card()
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dmac.h867 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) in rtw89_mac_reg_by_idx() argument
871 return band == 0 ? reg_base : (reg_base + mac->band1_offset); in rtw89_mac_reg_by_idx()
1029 u32 reg_base, u32 *cr);
1057 u32 reg_base, u32 *val) in rtw89_mac_txpwr_read32() argument
1061 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) in rtw89_mac_txpwr_read32()
1070 u32 reg_base, u32 val) in rtw89_mac_txpwr_write32() argument
1074 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) in rtw89_mac_txpwr_write32()
1083 u32 reg_base, u32 mask, u32 val) in rtw89_mac_txpwr_write32_mask() argument
1087 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) in rtw89_mac_txpwr_write32_mask()
/openbmc/linux/sound/soc/codecs/
H A Drt712-sdca-dmic.c262 regmap_read(rt712->mbq_regmap, p->reg_base + i, &regvalue); in rt712_sdca_dmic_set_gain_get()
297 regmap_read(rt712->mbq_regmap, p->reg_base + i, &regvalue[i]); in rt712_sdca_dmic_set_gain_put()
318 err = regmap_write(rt712->mbq_regmap, p->reg_base + i, gain_val[i]); in rt712_sdca_dmic_set_gain_put()
320 dev_err(&rt712->slave->dev, "0x%08x can't be set\n", p->reg_base + i); in rt712_sdca_dmic_set_gain_put()
398 {.reg_base = xreg_base, .count = xcount, .max = xmax, \
401 #define RT712_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \ argument
406 .private_value = RT712_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)}
408 #define RT712_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\ argument
416 .private_value = RT712_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) }
/openbmc/linux/drivers/irqchip/
H A Dirq-zevio.c44 readl(gc->reg_base + regs->ack); in zevio_irq_ack()
105 gc->reg_base = zevio_irq_io; in zevio_of_init()
H A Dirq-nvic.c115 gc->reg_base = nvic_base + 4 * i; in nvic_of_init()
126 writel_relaxed(~0, gc->reg_base + NVIC_ICER); in nvic_of_init()
/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh4.h173 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
179 return __raw_readl(chan->reg_base + reg); in pci_read_reg()
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_wopcm.c203 u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET); in __wopcm_regs_locked() local
207 !(reg_base & GUC_WOPCM_OFFSET_VALID)) in __wopcm_regs_locked()
210 *guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK; in __wopcm_regs_locked()

12345678910>>...19