| /openbmc/openpower-occ-control/service_files/ |
| H A D | op-occ-disable@.service | 5 Before=op-stop-instructions@%i.service
|
| /openbmc/linux/Documentation/arch/x86/ |
| H A D | tlb.rst | 15 time. This could potentially cost many more instructions, but
31 instructions have separate TLBs, as do different page sizes.
42 invlpg instruction (or instructions _near_ it) show up high in
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| /openbmc/linux/Documentation/admin-guide/hw-vuln/ |
| H A D | cross-thread-rsb.rst | 62 instructions with targeted return locations and then transitioning out of C0
70 targets by performing a sequence of CALL instructions.
73 intercepting HLT and MWAIT instructions.
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| /openbmc/linux/arch/arm/crypto/ |
| H A D | Kconfig | 28 - PMULL (Polynomial Multiply Long) instructions
80 BLAKE2b digest algorithm optimized with ARM NEON instructions.
229 - CRC and/or PMULL instructions
242 - PMULL (Polynomial Multiply Long) instructions
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| /openbmc/qemu/ |
| H A D | .gdbinit | 2 # follow the instructions it prints. They boil down to adding the following to
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| /openbmc/linux/arch/m68k/ifpsp060/ |
| H A D | isp.doc | 36 This exception is taken when any of the integer instructions
38 isp.sa provides full emulation support for these instructions.
40 The unimplemented integer instructions are:
174 The instructions "cas2" and "cas" (when used with a misaligned effective
176 060ISP is installed properly, these instructions will enter through the
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| /openbmc/openbmc/meta-openpower/recipes-phosphor/host/ |
| H A D | op-proc-control-systemd-links.bb | 23 LINK="$D$systemd_system_unitdir/obmc-host-stop@0.target.wants/op-stop-instructions@0.service"
24 TARGET="../op-stop-instructions@.service"
31 LINK="$D$systemd_system_unitdir/obmc-host-quiesce@0.target.wants/op-stop-instructions@0.service"
32 TARGET="../op-stop-instructions@.service"
137 LINK="$D$systemd_system_unitdir/obmc-host-stop@0.target.wants/op-stop-instructions@0.service"
|
| /openbmc/openbmc/poky/meta/files/common-licenses/ |
| H A D | Artistic-2.0 | 128 the Source, provided that you include complete instructions on how to
129 get the Source of the Standard Version. Such instructions must be
130 valid at the time of your distribution. If these instructions, at any
132 must provide new instructions on demand or cease further distribution.
133 If you provide valid instructions or cease distribution within thirty
134 days after you become aware that the instructions are invalid, then
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| /openbmc/linux/Documentation/staging/ |
| H A D | lzo.rst | 20 The stream is composed of a series of instructions, operands, and data. The
21 instructions consist in a few bits representing an opcode, and bits forming
29 as a piece of information for next instructions.
55 ranges, resulting in multiple copy instructions using different encodings.
74 In the code some length checks are missing because certain instructions
76 because it has already been guaranteed before parsing the instructions.
|
| /openbmc/openbmc/poky/meta/conf/machine/include/arm/ |
| H A D | arch-armv7m.inc | 6 TUNEVALID[armv7m] = "Enable instructions for ARMv7-m"
|
| H A D | arch-armv7em.inc | 6 TUNEVALID[armv7em] = "Enable instructions for ARMv7e-m"
|
| H A D | arch-armv8m-base.inc | 6 TUNEVALID[armv8m-base] = "Enable instructions for ARMv8-m.base"
|
| /openbmc/linux/arch/x86/math-emu/ |
| H A D | README | 154 an 80486DX. A 80486DX will allow some floating point instructions to
156 will not allow this in 16-bit protected mode: no instructions are
165 upon instruction mix. Relative performance is best for the instructions
166 which require most computation. The simple instructions are adversely
171 The times include load/store instructions. All times are in microseconds
233 these never exceeds 1/2 an lsb. The fprem and fprem1 instructions
316 The results show that the fsin, fcos and fptan instructions return
319 between -pi/2 and +pi/2. The other instructions have a lower
346 instructions return results which are in error for more than 10
351 was obtained per one million arguments. For three of the instructions,
[all …]
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| /openbmc/qemu/target/hexagon/imported/ |
| H A D | ldst.idef | 22 /* The set of addressing modes standard to all Load instructions */
33 /* The set of 32-bit load instructions */
41 /* These instructions do a load an unpack */
62 /* These instructions do a load an unpack */
115 /* The set of 32-bit store instructions */
240 /* The set of 32-bit predicated load instructions */
271 /* The set of 32-bit predicated store instructions */
322 /* The set of 32-bit store immediate instructions */
332 /* The set of 32-bit store immediate instructions */
352 /* The set of 32-bit load instructions */
[all …]
|
| /openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/ |
| H A D | Added-support-for-PPC-instructions-mfatbu-mfatbl.patch | 4 Subject: [PATCH] Added support for PPC instructions mfatbu, mfatbl.
6 Currently Valgrind 3.7.0 does not have support for PPC instructions mfatbu and mfatbl. When we run …
|
| /openbmc/qemu/docs/devel/ |
| H A D | tcg-ops.rst | 37 corresponds to a list of instructions terminated by a label, or
41 which corresponds to a list of instructions terminated by a label or
44 zero or more conditional branch instructions.
49 TCG instructions or *ops* operate on TCG *variables*, both of which
52 Vector instructions have a field specifying the element size within
186 When generating instructions, you can count on at least the following
189 - Single instructions are simplified, e.g.
199 another one. It is also used to remove instructions which compute
967 instructions. There is little performance advantage in using TCG to
968 implement guest instructions taking more than about twenty TCG
[all …]
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| /openbmc/linux/drivers/crypto/vmx/ |
| H A D | Kconfig | 12 Support for VMX cryptographic acceleration instructions on Power8 CPU.
|
| /openbmc/linux/arch/arm/nwfpe/ |
| H A D | ChangeLog | 74 * README.FPE - fix typo in description of lfm/sfm instructions
80 * README.FPE - fix description of URD, NRM instructions
81 * TODO - remove URD, NRM instructions from TODO list
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| /openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8a/ |
| H A D | tune-thunderx.inc | 4 TUNEVALID[thunderx] = "Enable instructions for Cavium ThunderX"
|
| /openbmc/u-boot/arch/riscv/ |
| H A D | Kconfig | 87 bool "Emit compressed instructions"
91 when building U-Boot, which results in compressed instructions in the
|
| /openbmc/openbmc/poky/documentation/dev-manual/ |
| H A D | intro.rst | 33 - Redundant step-by-step instructions: For example, the
35 instructions on how to install an SDK, which is used to develop
|
| /openbmc/qemu/target/arm/tcg/ |
| H A D | vfp-uncond.decode | 21 # Encodings for the unconditional VFP instructions are here:
27 # (but those patterns might also cover some Neon instructions,
|
| /openbmc/qemu/target/riscv/ |
| H A D | XVentanaCondOps.decode | 8 # Reference: VTx-family custom instructions
|
| /openbmc/linux/drivers/acpi/apei/ |
| H A D | apei-base.c | 46 u32 instructions, in apei_exec_ctx_init() argument
51 ctx->instructions = instructions; in apei_exec_ctx_init()
168 if (entry->instruction >= ctx->instructions || in __apei_exec_run()
210 if (ins >= ctx->instructions || !ins_table[ins].run) { in apei_exec_for_each_entry()
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| /openbmc/openpower-proc-control/service_files/ |
| H A D | op-stop-instructions@.service.in | 2 Description=Stop instructions for host%i
|