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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt4 RISC-V cores include Control Status Registers (CSRs) which are local to each
12 interrupts. Software interrupts are used to send IPIs between cores. The
H A Dopenrisc,ompic.txt7 size is based on the number of cores the controller has been configured
H A Dloongson,eiointc.yaml15 individual cores without forwarding them through the HT's interrupt line.
/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A Dl1d_flush.rst63 cores or by disabling SMT. See the relevant chapter in the L1TF mitigation
67 affinity is limited to cores running in non-SMT mode. If a task which
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A DKconfig4 tristate "ETNAVIV (DRM support for Vivante GPU IP cores)"
/openbmc/qemu/target/riscv/
H A DXVentanaCondOps.decode9 # Custom ISA extensions for Ventana Micro Systems RISC-V cores
/openbmc/linux/tools/perf/tests/
H A Dmake32 …cores := $(shell (getconf _NPROCESSORS_ONLN || grep -E -c '^processor|^CPU[0-9]' /proc/cpuinfo) 2>…
33 ifeq ($(cores),0)
34 cores := 1
37 cores=$(JOBS)
39 PARALLEL_OPT="-j$(cores)"
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dsunplus,sp7021.yaml14 ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC.
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992.dtsi8 /* 8992 only features 2 A57 cores. */
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-test/corstone1000-external-sys-tests/
H A Dcorstone1000-external-sys-tests_1.0.bb2 DESCRIPTION = "This is a Linux userspace tool to test the communication between Corstone1000 cores"
/openbmc/u-boot/doc/
H A DREADME.socfpga28 projects must have the IP cores updated as shown below.
42 Then (if necessary) update the IP cores in the project, generate HDL code, and
46 $ qsys-generate soc_system.qsys --upgrade-ip-cores
/openbmc/linux/Documentation/arch/x86/
H A Dbuslock.rst23 performance on other cores and brings the whole system to its knees.
84 time systems. These systems run hard real time code on some cores and run
85 "untrusted" user processes on other cores. The hard real time cannot afford
/openbmc/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst325 power among cores when there is a power constrained scenario. This defines a
673 also adjusts the priority of cores using Intel(R) Speed Select Technology Core
732 to cores based on the priority. By using this feature, some cores can be
734 the cost of lower or no turbo frequency on the low priority cores.
855 high-priority-cores-count:2
860 high-priority-cores-count:4
865 high-priority-cores-count:6
875 two high priority cores. If only two high priority cores are set, then max.
876 turbo frequency on those cores can be increased to 3200 MHz. This is 100 MHz
877 more than the base turbo capability for all cores.
[all …]
/openbmc/google-misc/subprojects/metrics-ipmi-blobs/
H A DREADME.md9 2. Uptime: uptime in wall clock time, idle process across all cores
/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,msm8976-ramp-controller.yaml15 CPU cores on some Qualcomm SoCs.
/openbmc/openbmc/poky/meta/recipes-support/liburcu/
H A Dliburcu_0.14.0.bb4 with the number of cores. "
/openbmc/linux/kernel/kcsan/
H A D.kunitconfig3 # option to configure a machine with several cores. For example:
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-r5f-rproc.yaml16 Split mode providing two individual compute cores for doubling the compute
29 the individual R5F cores. Each node has a number of required or optional
70 Configuration Mode for the Dual R5F cores within the R5F cluster.
105 The cores do not use an MMU, but has a Region Address Translator
173 # The following properties are optional properties for each of the R5F cores:
/openbmc/linux/arch/mips/include/asm/mach-cavium-octeon/
H A Dkernel-entry-init.h98 # All cores other than the master need to wait here for SMP bootstrap
141 # Someone tried to boot SMP with a non SMP kernel. All extra cores
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Drockchip-mailbox.txt3 The Rockchip mailbox is used by the Rockchip CPU cores to communicate
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dchip.c231 struct list_head cores; member
519 list_add_tail(&core->list, &ci->cores); in brcmf_chip_add_core()
532 list_for_each_entry(core, &ci->cores, list) { in brcmf_chip_cores_check()
1093 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list); in brcmf_chip_setup()
1143 INIT_LIST_HEAD(&chip->cores); in brcmf_chip_attach()
1175 list_for_each_entry_safe(core, tmp, &chip->cores, list) { in brcmf_chip_detach()
1188 list_for_each_entry(core, &chip->cores, list) { in brcmf_chip_get_d11core()
1203 list_for_each_entry(core, &chip->cores, list) in brcmf_chip_get_core()
1216 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list); in brcmf_chip_get_chipcommon()
/openbmc/linux/Documentation/devicetree/bindings/hwlock/
H A Dallwinner,sun6i-a31-hwspinlock.yaml13 The hardware unit provides semaphores between the ARM cores and the embedded
/openbmc/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dcpuctrl.yaml13 The clock registers and power registers of secondary cores are defined
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dmicrochip,mpfs-spi.yaml11 fabric IP cores they are based on
/openbmc/linux/sound/soc/intel/skylake/
H A Dcnl-sst.c203 cnl->cores.state[core_id] = SKL_DSP_RUNNING; in cnl_set_dsp_D0()
242 cnl->cores.state[core_id] = SKL_DSP_RUNNING; in cnl_set_dsp_D0()
283 cnl->cores.state[core_id] = SKL_DSP_RESET; in cnl_set_dsp_D3()

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