| /openbmc/linux/drivers/firmware/arm_scmi/ |
| H A D | clock.c | 102 struct scmi_clock_info *clk; member
172 clk->name, in scmi_clock_attributes_get()
300 .clk = clk, in scmi_clock_describe_rates_get()
317 clk->range.min_rate, clk->range.max_rate, in scmi_clock_describe_rates_get()
318 clk->range.step_size); in scmi_clock_describe_rates_get()
320 sort(clk->list.rates, clk->list.num_rates, in scmi_clock_describe_rates_get()
459 clk = ci->clk + clk_id; in scmi_clock_info_get()
460 if (!clk->name[0]) in scmi_clock_info_get()
463 return clk; in scmi_clock_info_get()
596 if (!cinfo->clk) in scmi_clock_protocol_init()
[all …]
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | clk-branch.h | 52 struct clk_branch clk, bool on) in qcom_branch_set_force_mem_core() argument
54 regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_CORE_ON, in qcom_branch_set_force_mem_core()
59 struct clk_branch clk, bool on) in qcom_branch_set_force_periph_on() argument
61 regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_ON, in qcom_branch_set_force_periph_on()
66 struct clk_branch clk, bool on) in qcom_branch_set_force_periph_off() argument
68 regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_OFF, in qcom_branch_set_force_periph_off()
72 static inline void qcom_branch_set_wakeup(struct regmap *regmap, struct clk_branch clk, u32 val) in qcom_branch_set_wakeup() argument
74 regmap_update_bits(regmap, clk.halt_reg, CBCR_WAKEUP, in qcom_branch_set_wakeup()
78 static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branch clk, u32 val) in qcom_branch_set_sleep() argument
80 regmap_update_bits(regmap, clk.halt_reg, CBCR_SLEEP, in qcom_branch_set_sleep()
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| /openbmc/u-boot/drivers/usb/phy/ |
| H A D | twl4030.c | 105 u8 pwr, clk; in twl4030_phy_power() local
112 clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); in twl4030_phy_power()
113 clk |= CLOCKGATING_EN | CLK32K_EN; in twl4030_phy_power()
114 twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); in twl4030_phy_power()
126 u8 clk, sts, pwr; in twl4030_usb_ulpi_init() local
135 clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); in twl4030_usb_ulpi_init()
136 clk |= REQ_PHY_DPLL_CLK; in twl4030_usb_ulpi_init()
137 twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); in twl4030_usb_ulpi_init()
170 clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); in twl4030_usb_ulpi_init()
171 clk &= ~REQ_PHY_DPLL_CLK; in twl4030_usb_ulpi_init()
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | allwinner,sun8i-a83t-de2-clk.yaml | 22 - const: allwinner,sun8i-a83t-de2-clk
23 - const: allwinner,sun8i-h3-de2-clk
24 - const: allwinner,sun8i-v3s-de2-clk
25 - const: allwinner,sun50i-a64-de2-clk
26 - const: allwinner,sun50i-h5-de2-clk
27 - const: allwinner,sun50i-h6-de3-clk
29 - const: allwinner,sun8i-r40-de2-clk
30 - const: allwinner,sun8i-h3-de2-clk
32 - const: allwinner,sun20i-d1-de2-clk
33 - const: allwinner,sun50i-h5-de2-clk
[all …]
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| H A D | allwinner,sun4i-a10-pll1-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
45 clk@1c20000 {
47 compatible = "allwinner,sun4i-a10-pll1-clk";
54 clk@1c20000 {
56 compatible = "allwinner,sun6i-a31-pll1-clk";
63 clk@1c20000 {
65 compatible = "allwinner,sun8i-a23-pll1-clk";
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| /openbmc/linux/drivers/soc/imx/ |
| H A D | soc-imx8m.c | 60 struct clk *clk; in imx8mq_soc_revision() local
69 if (IS_ERR(clk)) { in imx8mq_soc_revision()
70 WARN_ON(IS_ERR(clk)); in imx8mq_soc_revision()
74 clk_prepare_enable(clk); in imx8mq_soc_revision()
91 clk_disable_unprepare(clk); in imx8mq_soc_revision()
92 clk_put(clk); in imx8mq_soc_revision()
103 struct clk *clk; in imx8mm_soc_uid() local
114 if (IS_ERR(clk)) { in imx8mm_soc_uid()
115 WARN_ON(IS_ERR(clk)); in imx8mm_soc_uid()
119 clk_prepare_enable(clk); in imx8mm_soc_uid()
[all …]
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | stih407-clock.dtsi | 10 clk_sysin: clk-sysin {
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
41 clk_m_a9: clk-m-a9 {
53 arm_periph_clk: clk-m-a9-periphs {
68 clk_s_a0_pll: clk-s-a0-pll {
75 clk_s_a0_flexgen: clk-s-a0-flexgen {
89 clk_s_c0_pll0: clk-s-c0-pll0 {
96 clk_s_c0_pll1: clk-s-c0-pll1 {
103 clk_s_c0_quadfs: clk-s-c0-quadfs {
143 clk_s_d0_quadfs: clk-s-d0-quadfs {
[all …]
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | clock_sun6i.c | 110 void clock_set_pll1(unsigned int clk) in clock_set_pll1() argument
118 if (clk > 1152000000) { in clock_set_pll1()
120 } else if (clk > 768000000) { in clock_set_pll1()
148 void clock_set_pll3(unsigned int clk) in clock_set_pll3() argument
158 if (clk == 0) { in clock_set_pll3()
202 if (clk > 24000000 * k * max_n / m) { in clock_set_pll5()
204 if (clk > 24000000 * k * max_n / m) in clock_set_pll5()
226 clk /= 1000; in clock_set_mipi_pll()
234 if (value > clk) in clock_set_mipi_pll()
237 diff = clk - value; in clock_set_mipi_pll()
[all …]
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| /openbmc/u-boot/drivers/clk/altera/ |
| H A D | clk-arria10.c | 40 static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk) in socfpga_a10_clk_get_upstream() argument
73 dev_err(clk->dev, "Invalid clock source\n"); in socfpga_a10_clk_get_upstream()
81 static int socfpga_a10_clk_endisable(struct clk *clk, bool enable) in socfpga_a10_clk_endisable() argument
84 struct clk *upclk = NULL; in socfpga_a10_clk_endisable()
107 static int socfpga_a10_clk_enable(struct clk *clk) in socfpga_a10_clk_enable() argument
109 return socfpga_a10_clk_endisable(clk, true); in socfpga_a10_clk_enable()
112 static int socfpga_a10_clk_disable(struct clk *clk) in socfpga_a10_clk_disable() argument
114 return socfpga_a10_clk_endisable(clk, false); in socfpga_a10_clk_disable()
117 static ulong socfpga_a10_clk_get_rate(struct clk *clk) in socfpga_a10_clk_get_rate() argument
120 struct clk *upclk = NULL; in socfpga_a10_clk_get_rate()
[all …]
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | omap_hwmod_2430_data.c | 379 .clk = "core_l3_ck",
387 .clk = "i2c1_ick",
395 .clk = "i2c2_ick",
403 .clk = "usb_l4_ick",
411 .clk = "mmchs1_ick",
451 .clk = "gpios_ick",
459 .clk = "gpios_ick",
467 .clk = "gpios_ick",
475 .clk = "gpios_ick",
483 .clk = "gpio5_ick",
[all …]
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| /openbmc/linux/drivers/pwm/ |
| H A D | pwm-fsl-ftm.c | 50 struct clk *ipg_clk;
51 struct clk *clk[FSL_PWM_CLK_MAX]; member
137 c = clk_get_rate(fpc->clk[index]); in fsl_pwm_calculate_period_clk()
262 clk_disable_unprepare(fpc->clk[oldclk]); in fsl_pwm_apply_config()
421 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { in fsl_pwm_probe()
423 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); in fsl_pwm_probe()
427 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) in fsl_pwm_probe()
431 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) in fsl_pwm_probe()
434 fpc->clk[FSL_PWM_CLK_CNTEN] = in fsl_pwm_probe()
436 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) in fsl_pwm_probe()
[all …]
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| H A D | pwm-jz4740.c | 53 struct clk *clk; in jz4740_pwm_request() local
62 clk = clk_get(chip->dev, name); in jz4740_pwm_request()
63 if (IS_ERR(clk)) { in jz4740_pwm_request()
65 return PTR_ERR(clk); in jz4740_pwm_request()
68 err = clk_prepare_enable(clk); in jz4740_pwm_request()
70 clk_put(clk); in jz4740_pwm_request()
74 pwm_set_chip_data(pwm, clk); in jz4740_pwm_request()
81 struct clk *clk = pwm_get_chip_data(pwm); in jz4740_pwm_free() local
83 clk_disable_unprepare(clk); in jz4740_pwm_free()
84 clk_put(clk); in jz4740_pwm_free()
[all …]
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| /openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
| H A D | lpc32xx.dtsi | 68 clocks = <&clk LPC32XX_CLK_SLC>;
76 clocks = <&clk LPC32XX_CLK_MLC>;
84 clocks = <&clk LPC32XX_CLK_DMA>;
139 clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
148 clocks = <&clk LPC32XX_CLK_MAC>;
155 clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
181 clocks = <&clk LPC32XX_CLK_SSP0>;
191 clocks = <&clk LPC32XX_CLK_SPI1>;
232 clocks = <&clk LPC32XX_CLK_SD>;
322 clk: clock-controller@0 { label
[all …]
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| H A D | clk.c | 12 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; variable
16 if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397) in get_sys_clk_rate()
38 val = readl(&clk->hclkpll_ctrl); in get_hclk_pll_rate()
73 val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK; in get_hclk_clk_div()
87 val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK; in get_periph_clk_div()
94 if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN)) in get_periph_clk_rate()
104 if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN)) in get_sdram_clk_rate()
109 if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) { in get_sdram_clk_rate()
111 switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) { in get_sdram_clk_rate()
121 switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) { in get_sdram_clk_rate()
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| /openbmc/linux/arch/mips/loongson64/ |
| H A D | time.c | 19 struct clk *clk; in plat_time_init() local
31 clk = of_clk_get(np, 0); in plat_time_init()
32 if (IS_ERR(clk)) { in plat_time_init()
33 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); in plat_time_init()
37 cpu_clock_freq = clk_get_rate(clk); in plat_time_init()
38 clk_put(clk); in plat_time_init()
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk.h | 91 struct clk *tegra_clk_register_sync_source(const char *name,
134 struct clk *tegra_clk_register_divider(const char *name,
518 struct clk *tegra_clk_register_pll_out(const char *name,
633 struct clk *tegra_clk_register_periph(const char *name,
758 struct clk *tegra_clk_register_super_mux(const char *name,
762 struct clk *tegra_clk_register_super_clk(const char *name,
766 struct clk *tegra_clk_register_super_cclk(const char *name,
846 struct clk *clks[], int clk_max);
849 struct clk *clks[], int clk_max);
885 static inline struct clk *
[all …]
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| H A D | clk.c | 31 static struct clk **clks;
260 struct clk *clk; in tegra_init_dup_clks() local
263 clk = clks[dup_list->clk_id]; in tegra_init_dup_clks()
264 dup_list->lookup.clk = clk; in tegra_init_dup_clks()
272 struct clk *clk; in tegra_init_from_table() local
275 clk = clks[tbl->clk_id]; in tegra_init_from_table()
276 if (IS_ERR_OR_NULL(clk)) { in tegra_init_from_table()
289 __clk_get_name(clk)); in tegra_init_from_table()
298 __clk_get_name(clk)); in tegra_init_from_table()
303 if (clk_prepare_enable(clk)) { in tegra_init_from_table()
[all …]
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-pxa.c | 179 struct clk *clk; in pxa_timer_dt_init() local
189 clk = of_clk_get(np, 0); in pxa_timer_dt_init()
190 if (IS_ERR(clk)) { in pxa_timer_dt_init()
192 return PTR_ERR(clk); in pxa_timer_dt_init()
195 ret = clk_prepare_enable(clk); in pxa_timer_dt_init()
208 return pxa_timer_common_init(irq, clk_get_rate(clk)); in pxa_timer_dt_init()
217 struct clk *clk; in pxa_timer_nodt_init() local
220 clk = clk_get(NULL, "OSTIMER0"); in pxa_timer_nodt_init()
221 if (clk && !IS_ERR(clk)) { in pxa_timer_nodt_init()
222 clk_prepare_enable(clk); in pxa_timer_nodt_init()
[all …]
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| /openbmc/linux/arch/sh/boards/mach-sdk7786/ |
| H A D | setup.c | 164 static int sdk7786_pcie_clk_enable(struct clk *clk) in sdk7786_pcie_clk_enable() argument
170 static void sdk7786_pcie_clk_disable(struct clk *clk) in sdk7786_pcie_clk_disable() argument
180 static struct clk sdk7786_pcie_clk = {
186 .clk = &sdk7786_pcie_clk,
191 struct clk *clk; in sdk7786_clk_init() local
201 clk = clk_get(NULL, "extal"); in sdk7786_clk_init()
202 if (IS_ERR(clk)) in sdk7786_clk_init()
203 return PTR_ERR(clk); in sdk7786_clk_init()
204 ret = clk_set_rate(clk, 33333333); in sdk7786_clk_init()
205 clk_put(clk); in sdk7786_clk_init()
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| /openbmc/linux/arch/mips/ralink/ |
| H A D | clk.c | 66 struct clk *clk; in plat_time_init() local
79 clk = of_clk_get_from_provider(&clkspec); in plat_time_init()
80 if (IS_ERR(clk)) in plat_time_init()
81 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); in plat_time_init()
82 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); in plat_time_init()
83 mips_hpt_frequency = clk_get_rate(clk) / 2; in plat_time_init()
84 clk_put(clk); in plat_time_init()
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| /openbmc/u-boot/drivers/clk/renesas/ |
| H A D | renesas-cpg-mssr.h | 106 bool renesas_clk_is_mod(struct clk *clk);
107 int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
109 int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
111 int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
112 struct clk *parent);
113 int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
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| /openbmc/linux/drivers/clk/renesas/ |
| H A D | clk-emev2.c | 67 struct clk *clk; in emev2_smu_clkdiv_init() local
73 clk = clk_register_divider(NULL, np->name, parent_name, 0, in emev2_smu_clkdiv_init()
75 of_clk_add_provider(np, of_clk_src_simple_get, clk); in emev2_smu_clkdiv_init()
76 pr_debug("## %s %pOFn %p\n", __func__, np, clk); in emev2_smu_clkdiv_init()
84 struct clk *clk; in emev2_smu_gclk_init() local
90 clk = clk_register_gate(NULL, np->name, parent_name, 0, in emev2_smu_gclk_init()
92 of_clk_add_provider(np, of_clk_src_simple_get, clk); in emev2_smu_gclk_init()
93 pr_debug("## %s %pOFn %p\n", __func__, np, clk); in emev2_smu_gclk_init()
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| /openbmc/linux/drivers/clk/ti/ |
| H A D | clkt_iclk.c | 28 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) in omap2_clkt_iclk_allow_idle() argument
33 memcpy(&r, &clk->enable_reg, sizeof(r)); in omap2_clkt_iclk_allow_idle()
37 v |= (1 << clk->enable_bit); in omap2_clkt_iclk_allow_idle()
42 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) in omap2_clkt_iclk_deny_idle() argument
47 memcpy(&r, &clk->enable_reg, sizeof(r)); in omap2_clkt_iclk_deny_idle()
52 v &= ~(1 << clk->enable_bit); in omap2_clkt_iclk_deny_idle()
68 static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, in omap2430_clk_i2chs_find_idlest() argument
73 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); in omap2430_clk_i2chs_find_idlest()
75 *idlest_bit = clk->enable_bit; in omap2430_clk_i2chs_find_idlest()
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| /openbmc/linux/drivers/clk/x86/ |
| H A D | clk-pmc-atom.c | 32 struct clk_hw *clk; member
97 spin_lock_irqsave(&clk->lock, flags); in plt_clk_reg_update()
99 tmp = readl(clk->reg); in plt_clk_reg_update()
101 writel(tmp, clk->reg); in plt_clk_reg_update()
108 struct clk_plt *clk = to_clk_plt(hw); in plt_clk_set_parent() local
117 struct clk_plt *clk = to_clk_plt(hw); in plt_clk_get_parent() local
120 value = readl(clk->reg); in plt_clk_get_parent()
127 struct clk_plt *clk = to_clk_plt(hw); in plt_clk_enable() local
146 value = readl(clk->reg); in plt_clk_is_enabled()
226 if (IS_ERR(pclk->clk)) in plt_clk_register_fixed_rate()
[all …]
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| /openbmc/linux/drivers/clk/st/ |
| H A D | clkgen-pll.c | 650 struct clk *clk; in clkgen_pll_register() local
672 return clk; in clkgen_pll_register()
680 return clk; in clkgen_pll_register()
706 struct clk *clk; in clkgen_odf_register() local
739 if (IS_ERR(clk)) in clkgen_odf_register()
740 return clk; in clkgen_odf_register()
746 return clk; in clkgen_odf_register()
753 struct clk *clk; in clkgen_c32_pll_setup() local
773 if (IS_ERR(clk)) in clkgen_c32_pll_setup()
792 struct clk *clk; in clkgen_c32_pll_setup() local
[all …]
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