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Searched refs:caches (Results 26 – 50 of 207) sorted by relevance

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/openbmc/linux/arch/arm/mm/
H A Dproc-arm925.S84 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
436 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
443 mov r0, #4 @ disable write-back on caches explicitly
H A Dproc-arm1020e.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
415 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm922.S63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
380 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm1022.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
408 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-arm1026.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
397 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-xsc3.S92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
430 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
450 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
H A Dproc-arm1020.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
433 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dproc-xscale.S128 mcr p15, 0, r0, c1, c0, 0 @ disable caches
156 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
547 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
561 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
H A Dproc-feroceon.S79 mcr p15, 0, r0, c1, c0, 0 @ disable caches
95 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
524 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
537 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
H A Dpv-fixup-asm.S23 bic ip, r8, #CR_M @ disable caches and MMU
/openbmc/linux/Documentation/filesystems/nfs/
H A Drpc-cache.rst13 a wide variety of values to be caches.
15 There are a number of caches that are similar in structure though
17 of common code for managing these caches.
19 Examples of caches that are likely to be needed are:
105 includes it on a list of caches that will be regularly
/openbmc/openbmc/poky/meta/recipes-core/systemd/systemd/
H A D0020-sd-event-Make-malloc_trim-conditional-on-glibc.patch25 …* A default implementation of a memory pressure callback. Simply releases our own allocation caches
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-core/sdbus-c++/sdbus-c++-libsystemd/
H A D0020-sd-event-Make-malloc_trim-conditional-on-glibc.patch25 …* A default implementation of a memory pressure callback. Simply releases our own allocation caches
/openbmc/linux/tools/testing/selftests/zram/
H A DREADME9 use as swap disks, various caches under /var and maybe many more :)
/openbmc/linux/drivers/cxl/
H A DKconfig131 the content of CPU caches without notifying those caches to
133 to invalidate caches when those events occur. If that invalidation
/openbmc/linux/Documentation/mm/
H A Dslub.rst7 slab caches. SLUB always includes full debugging but it is off by default.
56 O Switch debugging off for caches that would have
82 a result of storing the metadata (for example, caches with PAGE_SIZE object
85 switch off debugging for such caches by default, use::
95 You can also enable options (e.g. sanity checks and poisoning) for all caches
391 For more information about current state of SLUB caches with the user tracking
393 /sys/kernel/debug/slab/<cache>/ (created only for caches with enabled user
/openbmc/linux/Documentation/locking/
H A Dpercpu-rw-semaphore.rst10 is bouncing between L1 caches of the cores, causing performance
/openbmc/linux/fs/coda/
H A DKconfig12 persistent client caches and write back caching.
/openbmc/linux/tools/perf/util/
H A Dheader.c1241 caches[*cntp] = c; in build_caches_for_cpu()
1270 struct cpu_cache_level caches[max_caches]; in write_cache() local
1274 ret = build_caches(caches, &cnt); in write_cache()
1289 struct cpu_cache_level *c = &caches[i]; in write_cache()
1315 cpu_cache_level__free(&caches[i]); in write_cache()
2901 struct cpu_cache_level *caches; in process_cache() local
2913 caches = zalloc(sizeof(*caches) * cnt); in process_cache()
2914 if (!caches) in process_cache()
2940 caches[i] = c; in process_cache()
2943 ff->ph->env.caches = caches; in process_cache()
[all …]
H A Denv.h86 struct cpu_cache_level *caches; member
/openbmc/linux/fs/fscache/
H A DKconfig9 Different sorts of caches can be plugged in, depending on the
/openbmc/linux/drivers/scsi/qla2xxx/
H A DKconfig25 Upon request, the driver caches the firmware image until
/openbmc/linux/Documentation/core-api/
H A Dcachetlb.rst125 us to properly handle systems whose caches are strict and require
133 indexed caches which must be flushed when virtual-->physical
135 indexed physically tagged caches of IA32 processors have no need to
136 implement these interfaces since the caches are fully synchronized
144 the caches. That is, after running, there will be no cache
153 the caches. That is, after running, there will be no cache
160 optimizations for VIPT caches.
/openbmc/openbmc/poky/documentation/toaster-manual/
H A Dstart.rst43 Python 3 cache in your ``$HOME`` directory. The caches is actually
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpamu.txt61 second is the number of "ways". For direct-mapped caches,
67 second is the number of "ways". For direct-mapped caches,

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