1d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 2d8dc7fbdSRussell King/* 3d8dc7fbdSRussell King * Copyright (C) 2015 Russell King 4d8dc7fbdSRussell King * 5d8dc7fbdSRussell King * This assembly is required to safely remap the physical address space 6d8dc7fbdSRussell King * for Keystone 2 7d8dc7fbdSRussell King */ 8d8dc7fbdSRussell King#include <linux/linkage.h> 965fddcfcSMike Rapoport#include <linux/pgtable.h> 10d8dc7fbdSRussell King#include <asm/asm-offsets.h> 11d8dc7fbdSRussell King#include <asm/cp15.h> 12*a9ff6961SLinus Walleij#include <asm/page.h> 13d8dc7fbdSRussell King 14d8dc7fbdSRussell King .section ".idmap.text", "ax" 15d8dc7fbdSRussell King 16d8dc7fbdSRussell King#define L1_ORDER 3 17d8dc7fbdSRussell King#define L2_ORDER 3 18d8dc7fbdSRussell King 19d8dc7fbdSRussell KingENTRY(lpae_pgtables_remap_asm) 20d8dc7fbdSRussell King stmfd sp!, {r4-r8, lr} 21d8dc7fbdSRussell King 22d8dc7fbdSRussell King mrc p15, 0, r8, c1, c0, 0 @ read control reg 23d8dc7fbdSRussell King bic ip, r8, #CR_M @ disable caches and MMU 24d8dc7fbdSRussell King mcr p15, 0, ip, c1, c0, 0 25d8dc7fbdSRussell King dsb 26d8dc7fbdSRussell King isb 27d8dc7fbdSRussell King 28d8dc7fbdSRussell King /* Update level 2 entries covering the kernel */ 29d8dc7fbdSRussell King ldr r6, =(_end - 1) 30d8dc7fbdSRussell King add r7, r2, #0x1000 31d8dc7fbdSRussell King add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER 32463dbba4SLinus Walleij add r7, r7, #KERNEL_OFFSET >> (SECTION_SHIFT - L2_ORDER) 33bc2eca9aSNicolas Pitre1: ldrd r4, r5, [r7] 34d8dc7fbdSRussell King adds r4, r4, r0 35d8dc7fbdSRussell King adc r5, r5, r1 36bc2eca9aSNicolas Pitre strd r4, r5, [r7], #1 << L2_ORDER 37d8dc7fbdSRussell King cmp r7, r6 38d8dc7fbdSRussell King bls 1b 39d8dc7fbdSRussell King 40d8dc7fbdSRussell King /* Update level 2 entries for the boot data */ 41d8dc7fbdSRussell King add r7, r2, #0x1000 427a1be318SArd Biesheuvel movw r3, #FDT_FIXED_BASE >> (SECTION_SHIFT - L2_ORDER) 437a1be318SArd Biesheuvel add r7, r7, r3 44bc2eca9aSNicolas Pitre ldrd r4, r5, [r7] 45d8dc7fbdSRussell King adds r4, r4, r0 46d8dc7fbdSRussell King adc r5, r5, r1 47bc2eca9aSNicolas Pitre strd r4, r5, [r7], #1 << L2_ORDER 48bc2eca9aSNicolas Pitre ldrd r4, r5, [r7] 49d8dc7fbdSRussell King adds r4, r4, r0 50d8dc7fbdSRussell King adc r5, r5, r1 51bc2eca9aSNicolas Pitre strd r4, r5, [r7] 52d8dc7fbdSRussell King 53d8dc7fbdSRussell King /* Update level 1 entries */ 54d8dc7fbdSRussell King mov r6, #4 55d8dc7fbdSRussell King mov r7, r2 56bc2eca9aSNicolas Pitre2: ldrd r4, r5, [r7] 57d8dc7fbdSRussell King adds r4, r4, r0 58d8dc7fbdSRussell King adc r5, r5, r1 59bc2eca9aSNicolas Pitre strd r4, r5, [r7], #1 << L1_ORDER 60d8dc7fbdSRussell King subs r6, r6, #1 61d8dc7fbdSRussell King bne 2b 62d8dc7fbdSRussell King 63d8dc7fbdSRussell King mrrc p15, 0, r4, r5, c2 @ read TTBR0 64d8dc7fbdSRussell King adds r4, r4, r0 @ update physical address 65d8dc7fbdSRussell King adc r5, r5, r1 66d8dc7fbdSRussell King mcrr p15, 0, r4, r5, c2 @ write back TTBR0 67d8dc7fbdSRussell King mrrc p15, 1, r4, r5, c2 @ read TTBR1 68d8dc7fbdSRussell King adds r4, r4, r0 @ update physical address 69d8dc7fbdSRussell King adc r5, r5, r1 70d8dc7fbdSRussell King mcrr p15, 1, r4, r5, c2 @ write back TTBR1 71d8dc7fbdSRussell King 72d8dc7fbdSRussell King dsb 73d8dc7fbdSRussell King 74d8dc7fbdSRussell King mov ip, #0 75d8dc7fbdSRussell King mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate 76d8dc7fbdSRussell King mcr p15, 0, ip, c8, c7, 0 @ local_flush_tlb_all() 77d8dc7fbdSRussell King dsb 78d8dc7fbdSRussell King isb 79d8dc7fbdSRussell King 80d8dc7fbdSRussell King mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU 81d8dc7fbdSRussell King dsb 82d8dc7fbdSRussell King isb 83d8dc7fbdSRussell King 84d8dc7fbdSRussell King ldmfd sp!, {r4-r8, pc} 85d8dc7fbdSRussell KingENDPROC(lpae_pgtables_remap_asm) 86