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/openbmc/openbmc-tools/ipkdbg/
H A Dipkdbg.in290 local cache="$(ipkdbg_opkg_conf_gen_cache $build)"
291 mkdir -p $(dirname $cache)
293 ipkdbg_opkg_fetch_path "$(ipkdbg_opkg_conf_gen_path $build)" $cache ||
319 local cache="$(ipkdbg_opkg_db_gen_cache $build)"
321 if ! [ -f $cache ]
323 mkdir -p $(dirname $cache)
324 ipkdbg_opkg_fetch_path "$(ipkdbg_opkg_db_gen_path $build)" $cache ||
325 ipkdbg_opkg_fetch_url "$(ipkdbg_opkg_db_gen_url $build)" $cache ||
326 rm -f $cache
328 tar -xf $cache -C $state 2> /dev/null
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/openbmc/linux/arch/arm/mm/
H A Dcache-v7.S43 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
45 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR
112 beq start_flush_levels @ start flushing cache levels
133 mov r10, #0 @ start clean at cache level 0
136 mov r1, r0, lsr r2 @ extract cache type bits from clidr
138 cmp r1, #2 @ see what cache we have at this level
139 blt skip @ skip if no cache, or just i-cache
149 and r2, r1, #7 @ extract the length of the cache lines
164 orr r5, r5, r10 @ factor cache level into r5
171 add r10, r10, #2 @ increment cache number
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/openbmc/linux/arch/mips/kernel/
H A Dcacheinfo.c8 #define populate_cache(cache, leaf, c_level, c_type) \ argument
12 leaf->coherency_line_size = c->cache.linesz; \
13 leaf->number_of_sets = c->cache.sets; \
14 leaf->ways_of_associativity = c->cache.ways; \
15 leaf->size = c->cache.linesz * c->cache.sets * \
16 c->cache.ways; \
/openbmc/linux/drivers/net/xen-netback/
H A Dhash.c50 spin_lock_irqsave(&vif->hash.cache.lock, flags); in xenvif_add_hash()
55 lockdep_is_held(&vif->hash.cache.lock)) { in xenvif_add_hash()
65 new->seq = atomic_inc_return(&vif->hash.cache.seq); in xenvif_add_hash()
66 list_add_rcu(&new->link, &vif->hash.cache.list); in xenvif_add_hash()
70 vif->hash.cache.count--; in xenvif_add_hash()
104 spin_lock_irqsave(&vif->hash.cache.lock, flags); in xenvif_flush_hash()
107 lockdep_is_held(&vif->hash.cache.lock)) { in xenvif_flush_hash()
109 vif->hash.cache.count--; in xenvif_flush_hash()
459 BUG_ON(vif->hash.cache.count); in xenvif_init_hash()
461 spin_lock_init(&vif->hash.cache.lock); in xenvif_init_hash()
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/openbmc/linux/mm/kasan/
H A Dkasan_test.c731 struct kmem_cache *cache; in kmem_cache_oob() local
745 kmem_cache_free(cache, p); in kmem_cache_oob()
746 kmem_cache_destroy(cache); in kmem_cache_oob()
754 struct kmem_cache *cache; in kmem_cache_accounted() local
773 kmem_cache_destroy(cache); in kmem_cache_accounted()
778 struct kmem_cache *cache; in kmem_cache_bulk() local
798 kmem_cache_destroy(cache); in kmem_cache_bulk()
933 struct kmem_cache *cache; in kmem_cache_double_free() local
945 kmem_cache_free(cache, p); in kmem_cache_double_free()
954 struct kmem_cache *cache; in kmem_cache_invalid_free() local
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H A Dtags.c95 static void save_stack_info(struct kmem_cache *cache, void *object, in save_stack_info() argument
123 WRITE_ONCE(entry->size, cache->object_size); in save_stack_info()
136 void kasan_save_alloc_info(struct kmem_cache *cache, void *object, gfp_t flags) in kasan_save_alloc_info() argument
138 save_stack_info(cache, object, flags, false); in kasan_save_alloc_info()
141 void kasan_save_free_info(struct kmem_cache *cache, void *object) in kasan_save_free_info() argument
143 save_stack_info(cache, object, 0, true); in kasan_save_free_info()
/openbmc/pyphosphor/obmc/dbuslib/
H A Dintrospection.py24 self.cache = {}
56 if self.cache:
57 return self.cache
59 self.cache['interfaces'] = {}
60 self.cache['children'] = []
69 self.cache['interfaces'][name] = p.parse_interface()
71 self.cache['children'] = self.parse_children()
73 return self.cache
/openbmc/openbmc/poky/meta/recipes-core/glibc/ldconfig-native-2.12.1/
H A Dadd-riscv-support.patch14 cache.c | 6 ++++++
19 diff --git a/cache.c b/cache.c
21 --- a/cache.c
22 +++ b/cache.c
47 /* Name of auxiliary cache. */
48 #define _PATH_LDCONFIG_AUX_CACHE "/var/cache/ldconfig/aux-cache"
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi59 i-cache-sets = <256>;
62 d-cache-sets = <256>;
73 i-cache-sets = <256>;
76 d-cache-sets = <256>;
87 i-cache-sets = <256>;
90 d-cache-sets = <256>;
101 i-cache-sets = <256>;
104 d-cache-sets = <256>;
110 cache-level = <2>;
111 cache-unified;
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/openbmc/linux/Documentation/scsi/
H A Dsd-parameters.rst9 Enable/disable drive write & read cache.
12 cache_type string WCE RCD Write cache Read cache
20 To set cache type to "write back" and save this setting to the drive::
25 "temporary " to the cache type string. E.g.::
/openbmc/qemu/include/exec/
H A Dmemory.h2754 #define ARG1 cache
2763 if (likely(cache->ptr)) { in address_space_ldub_cached()
2774 if (likely(cache->ptr)) { in address_space_stb_cached()
2788 #define ARG1 cache
2827 cache->mrs.mr = NULL; in address_space_cache_init_empty()
2829 cache->fv = NULL; in address_space_cache_init_empty()
3023 assert(addr < cache->len && len <= cache->len - addr); in address_space_read_cached()
3024 fuzz_dma_read_cb(cache->xlat + addr, len, cache->mrs.mr); in address_space_read_cached()
3025 if (likely(cache->ptr)) { in address_space_read_cached()
3045 assert(addr < cache->len && len <= cache->len - addr); in address_space_write_cached()
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/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi68 i-cache-sets = <128>;
71 d-cache-sets = <128>;
86 i-cache-sets = <128>;
234 cache-level = <2>;
237 cache-sets = <512>;
239 cache-unified;
244 cache-level = <2>;
249 cache-unified;
252 l3_0: l3-cache {
254 cache-level = <3>;
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/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi3398 cache-unified;
3408 cache-unified;
3418 cache-unified;
3428 cache-unified;
3438 cache-unified;
3448 cache-unified;
3458 cache-unified;
3468 cache-unified;
3478 cache-unified;
3488 cache-unified;
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/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dcache.c63 static void get_cache_ways_sets(struct dcache_config *cache) in get_cache_ways_sets() argument
67 cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; in get_cache_ways_sets()
68 cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT; in get_cache_ways_sets()
172 struct dcache_config cache; in action_dcache_all() local
184 get_cache_ways_sets(&cache); /* Get number of ways & sets */ in action_dcache_all()
185 debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1); in action_dcache_all()
186 for (i = cache.sets; i >= 0; i--) { in action_dcache_all()
187 for (j = cache.ways; j >= 0; j--) { in action_dcache_all()
/openbmc/openbmc/poky/meta/recipes-core/systemd/systemd/
H A Dinit19 [ -f /etc/default/udev-cache ] && . /etc/default/udev-cache
58 readfile /etc/udev/cache.data
63 [ -e /dev/shm/udev.cache ] && rm -f /dev/shm/udev.cache
65 echo "$VERSION$CMDLINE$DEVICES$ATAGS" > /dev/shm/udev.cache
68 echo "$VERSION$CMDLINE$DEVICES$ATAGS" > /dev/shm/udev.cache
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12a.dtsi20 next-level-cache = <&l2>;
29 next-level-cache = <&l2>;
38 next-level-cache = <&l2>;
47 next-level-cache = <&l2>;
52 compatible = "cache";
53 cache-level = <2>;
54 cache-unified;
/openbmc/linux/Documentation/kernel-hacking/
H A Dfalse-sharing.rst9 False sharing is related with cache mechanism of maintaining the data
10 coherence of one cache line stored in multiple CPU's caches; then
20 Member 'refcount'(A) and 'name'(B) _share_ one cache line like below::
49 mm_struct struct, whose cache line layout change triggered a
75 purposely put in one cache line.
76 * global data being put together in one cache line. Some kernel
80 without being noticed (cache line is usually 64 bytes or more),
126 'pahole' decodes data structure layouts delimited in cache line
148 cache line and TLB entries.
184 * Be aware of cache line boundaries
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/openbmc/linux/net/rds/
H A Dib_recv.c93 tmp = xchg(&cache->xfer, NULL); in rds_ib_cache_xfer_to_ready()
95 if (cache->ready) in rds_ib_cache_xfer_to_ready()
98 cache->ready = tmp; in rds_ib_cache_xfer_to_ready()
108 if (!cache->percpu) in rds_ib_recv_alloc_cache()
116 cache->xfer = NULL; in rds_ib_recv_alloc_cache()
117 cache->ready = NULL; in rds_ib_recv_alloc_cache()
150 if (cache->ready) { in rds_ib_cache_splice_all_lists()
152 cache->ready = NULL; in rds_ib_cache_splice_all_lists()
506 old = xchg(&cache->xfer, NULL); in rds_ib_recv_cache_put()
525 cache->ready = head->next; in rds_ib_recv_cache_get()
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/openbmc/linux/include/net/
H A Dnetlabel.h198 struct netlbl_lsm_cache *cache; member
280 struct netlbl_lsm_cache *cache; in netlbl_secattr_cache_alloc() local
282 cache = kzalloc(sizeof(*cache), flags); in netlbl_secattr_cache_alloc()
283 if (cache) in netlbl_secattr_cache_alloc()
284 refcount_set(&cache->refcount, 1); in netlbl_secattr_cache_alloc()
285 return cache; in netlbl_secattr_cache_alloc()
298 if (!refcount_dec_and_test(&cache->refcount)) in netlbl_secattr_cache_free()
301 if (cache->free) in netlbl_secattr_cache_free()
302 cache->free(cache->data); in netlbl_secattr_cache_free()
303 kfree(cache); in netlbl_secattr_cache_free()
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/openbmc/linux/Documentation/admin-guide/device-mapper/
H A Dcache-policies.rst26 Overview of supplied cache replacement policies
56 mq policy's hints to be dropped. Also, performance of the cache may
63 The mq policy used a lot of memory; 88 bytes per cache block on a 64
70 cache block).
72 All this means smq uses ~25bytes per cache block. Still a lot of
91 The mq policy maintained a hit count for each cache block. For a
92 different block to get promoted to the cache its hit count has to
93 exceed the lowest currently in the cache. This meant it could take a
94 long time for the cache to adapt between varying IO patterns.
117 cache <metadata dev> <cache dev> <origin dev> <block size>
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/openbmc/linux/arch/s390/kernel/
H A Dcache.c70 struct cacheinfo *cache; in show_cacheinfo() local
75 cache = this_cpu_ci->info_list + idx; in show_cacheinfo()
77 seq_printf(m, "level=%d ", cache->level); in show_cacheinfo()
78 seq_printf(m, "type=%s ", cache_type_string[cache->type]); in show_cacheinfo()
80 cache->disable_sysfs ? "Shared" : "Private"); in show_cacheinfo()
81 seq_printf(m, "size=%dK ", cache->size >> 10); in show_cacheinfo()
82 seq_printf(m, "line_size=%u ", cache->coherency_line_size); in show_cacheinfo()
83 seq_printf(m, "associativity=%d", cache->ways_of_associativity); in show_cacheinfo()
/openbmc/linux/arch/sh/boot/dts/
H A Dj2_mimas_v2.dts22 d-cache-size = <8192>;
23 i-cache-size = <8192>;
24 d-cache-block-size = <16>;
25 i-cache-block-size = <16>;
57 cache-controller@c0 {
58 compatible = "jcore,cache";
/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
23 i-cache-sets = <128>;
24 i-cache-size = <32768>;
/openbmc/qemu/migration/
H A Dpage_cache.h36 void cache_fini(PageCache *cache);
47 bool cache_is_cached(const PageCache *cache, uint64_t addr,
58 uint8_t *get_cached_data(const PageCache *cache, uint64_t addr);
71 int cache_insert(PageCache *cache, uint64_t addr, const uint8_t *pdata,
/openbmc/linux/drivers/power/supply/
H A Dbq27xxx_battery.c1781 struct bq27xxx_reg_cache *cache) argument
1793 if (cache) {
1794 flags = cache->flags;
1842 if ((cache.flags & 0xff) == 0xff)
1843 cache.flags = -1; /* read error */
1844 if (cache.flags >= 0) {
1857 di->cache.flags = cache.flags;
1874 if ((di->cache.capacity != cache.capacity) ||
1875 (di->cache.flags != cache.flags) ||
1881 if (memcmp(&di->cache, &cache, sizeof(cache)) != 0)
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