| /openbmc/linux/Documentation/virt/kvm/x86/ |
| H A D | hypercalls.rst | 63 flushing TLB, release PT.
|
| /openbmc/qemu/target/s390x/ |
| H A D | cpu_features_def.h.inc | 26 DEF_FEAT(IDTE_SEGMENT, "idtes", STFL, 4, "IDTE selective TLB segment-table clearing")
27 DEF_FEAT(IDTE_REGION, "idter", STFL, 5, "IDTE selective TLB region-table clearing")
70 DEF_FEAT(LOCAL_TLB_CLEARING, "ltlbc", STFL, 51, "Local-TLB-clearing facility")
|
| /openbmc/linux/arch/powerpc/platforms/ |
| H A D | Kconfig.cputype | 66 bool "Support for 603 SW loaded TLB"
71 processors don't have a HASH MMU and provide SW TLB loading.
|
| /openbmc/u-boot/board/freescale/t4qds/ |
| H A D | README | 106 …0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB)
|
| /openbmc/linux/kernel/dma/ |
| H A D | Kconfig | 98 This enables dynamic resizing of the software IO TLB. The kernel
|
| /openbmc/openbmc/poky/meta/classes-recipe/ |
| H A D | qemuboot.bbclass | 115 # With 6.5+ (specifically, if DMA_BOUNCE_UNALIGNED_KMALLOC is set) the SW IO TLB
|
| /openbmc/linux/Documentation/timers/ |
| H A D | no_hz.rst | 295 OS jitter due to global TLB shootdowns is to avoid the unmapping
298 and TLB misses can be reduced (and in some cases eliminated) by
|
| /openbmc/linux/Documentation/mm/ |
| H A D | vmemmap_dedup.rst | 169 entries that can be cached in a single TLB entry.
|
| /openbmc/qemu/tcg/riscv/ |
| H A D | tcg-target.c.inc | 1171 * Load/store and TLB
1230 * For system-mode, perform the TLB load and compare.
1299 /* Compare masked address with the TLB entry. */
1303 /* TLB Hit - translate address using addend. */
|
| /openbmc/linux/arch/arm64/ |
| H A D | Kconfig | 705 TLB sequences to be done twice.
944 TLB sequences to be done twice.
1036 TLB invalidation, for all changes to executable user space mappings.
1183 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1226 invalidate shared TLB entries installed by a different core, as it would
1274 allowing only two levels of page tables and faster TLB
1864 caching of such entries in the TLB.
|
| /openbmc/u-boot/doc/ |
| H A D | README.sifive-fu540 | 179 [ 0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
|
| /openbmc/linux/Documentation/arch/ia64/ |
| H A D | aliasing.rst | 15 contained in the TLB entry. The ones of most interest to the Linux
|
| H A D | mca.rst | 92 radical surgery on the rest of ia64, plus extra hard wired TLB
|
| /openbmc/linux/Documentation/arch/sparc/ |
| H A D | adi.rst | 19 2. Set TTE.mcd bit on any TLB entries that correspond to the range of
|
| /openbmc/qemu/docs/devel/ |
| H A D | tcg.rst | 177 QEMU uses an address translation cache (TLB) to speed up the translation.
|
| /openbmc/linux/Documentation/virt/kvm/ |
| H A D | locking.rst | 196 writable spte might be cached on a CPU's TLB.
|
| /openbmc/linux/arch/arm/ |
| H A D | Kconfig | 732 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
733 As a consequence of this erratum, some TLB entries which should be
735 tables. The workaround changes the TLB flushing routines to invalidate
763 potentially leading to corrupted entries in the cache or TLB.
776 can populate the micro-TLB with a stale entry which may be hit with
|
| /openbmc/linux/Documentation/powerpc/ |
| H A D | transactional_memory.rst | 182 TM_CAUSE_TLBI Software TLB invalid.
|
| /openbmc/qemu/target/hppa/ |
| H A D | insns.decode | 158 # pcxl and pcxl2 Fast TLB Insert instructions
|
| /openbmc/linux/arch/arm/boot/compressed/ |
| H A D | head.S | 1184 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1198 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
|
| /openbmc/linux/Documentation/admin-guide/mm/ |
| H A D | hugetlbpage.rst | 13 256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
15 Operating systems try to make best use of limited number of TLB resources.
|
| /openbmc/linux/arch/powerpc/ |
| H A D | Kconfig | 898 memory. Aligning to 8M reduces TLB misses as only 8M pages are used
1214 the TLB page size of the mapping for kernel on the particular platform.
1215 Please refer to the init code for finding the TLB page size.
|
| /openbmc/u-boot/board/qualcomm/dragonboard820c/ |
| H A D | readme.txt | 337 [ 0.000000] software IO TLB [mem 0xd3fff000-0xd7fff000] (64MB) mapped at [ffff800053fff000-ffff8…
|
| /openbmc/linux/Documentation/admin-guide/ |
| H A D | sysrq.rst | 145 Dump all TLB entries on MIPS.
|
| /openbmc/linux/include/linux/ |
| H A D | perf_event.h | 1202 PERF_MEM_S(TLB, NA) |\
|