| /openbmc/linux/drivers/soc/rockchip/ |
| H A D | Kconfig | 9 bool "Rockchip General Register Files support" if COMPILE_TEST
12 The General Register Files are a central component providing
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| /openbmc/qemu/target/hexagon/imported/ |
| H A D | shift.idef | 32 "Arithmetic Shift Right by Register", \
39 "Arithmetic Shift Left by Register", \
46 "Logical Shift Right by Register", \
53 "Logical Shift Left by Register", \
75 /* Register shift with saturation */
78 "Arithmetic Shift Right by Register", \
85 "Arithmetic Shift Left by Register", \
127 "Logical Shift Right by Register", \
130 "Shift Left by Register", \
547 /* Half Vector Register Shifts */
[all …]
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | vfpmacros.h | 47 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
72 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
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| /openbmc/linux/Documentation/w1/slaves/ |
| H A D | w1_ds2438.rst | 30 Status/Configuration Register.
57 This file controls the 2-byte Offset Register of the chip.
58 Writing a 2-byte value will change the Offset Register, which changes the
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | renesas,cpg-mstp-clocks.yaml | 35 - description: Module Stop Control Register (MSTPCR)
36 - description: Module Stop Status Register (MSTPSR)
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| /openbmc/linux/Documentation/arch/xtensa/ |
| H A D | atomctl.rst | 2 Atomic Operation Control (ATOMCTL) Register
5 We Have Atomic Operation Control (ATOMCTL) Register.
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| /openbmc/qemu/docs/specs/ |
| H A D | fw_cfg.rst | 14 Selector (Control) Register
53 Data Register
84 Register Locations
88 * Selector Register IOport: 0x510
89 * Data Register IOport: 0x511
93 * Selector Register address: Base + 8 (2 bytes)
94 * Data Register address: Base + 0 (8 bytes)
119 Register returns 0x51454d5520434647 (``QEMU CFG`` in big-endian format).
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| H A D | ppc-xive.rst | 137 - Interrupt Priority Register (PIPR)
140 - Notification Source Register (NSR)
162 Interrupt Priority Register (PIPR) is also updated using the IPB. This
167 Register (CPPR). If it is more favored (numerically less than), the
169 Register (NSR) is updated to notify the presence of an exception for
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | starfive,jh7110-usb.yaml | 22 - description: phandle to System Register Controller stg_syscon node.
25 The phandle to System Register Controller syscon node and the offset
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| /openbmc/linux/Documentation/devicetree/bindings/leds/ |
| H A D | register-bit-led.yaml | 7 title: Register Bit LEDs
13 Register bit leds are used with syscon multifunctional devices where single
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | fsl,ls-extirq.yaml | 46 Specifies the Interrupt Polarity Control Register (INTPCR) in the
47 SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-coresight-devices-etm4x | 343 Description: (Read) Print the content of the Power Down Control Register
350 Description: (Read) Print the content of the Power Down Status Register
357 Description: (Read) Print the content of the SW Lock Status Register
364 Description: (Read) Print the content of the Authentication Status Register
371 Description: (Read) Print the content of the Device ID Register
378 Description: (Read) Print the content of the Device Architecture Register
386 Description: (Read) Print the content of the Device Type Register
393 Description: (Read) Print the content of the Peripheral ID0 Register
400 Description: (Read) Print the content of the Peripheral ID1 Register
407 Description: (Read) Print the content of the Peripheral ID2 Register
[all …]
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| H A D | sysfs-bus-i3c | 50 BCR stands for Bus Characteristics Register and express the
60 DCR stands for Device Characteristics Register and express the
110 BCR stands for Bus Characteristics Register and express the
118 DCR stands for Device Characteristics Register and express the
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| /openbmc/linux/Documentation/admin-guide/hw-vuln/ |
| H A D | reg-file-data-sampling.rst | 2 Register File Data Sampling (RFDS)
5 Register File Data Sampling (RFDS) is a microarchitectural vulnerability that
97 * - 'Mitigation: Clear Register File'
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| /openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | cdns,dsi.yaml | 25 Register block for controller's registers.
27 Register block for wrapper settings registers in case of TI J7 SoCs.
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| /openbmc/linux/arch/arm/mach-shmobile/ |
| H A D | headsmp-scu.S | 24 ldr r2, [r0, #8] @ SCU Power Status Register
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | omap-dmic.txt | 5 - reg: Register location and size as an array:
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| H A D | apple,mca.yaml | 31 - description: Register region of the MCA clusters proper
32 - description: Register region of the DMA glue and its FIFOs
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| /openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/ |
| H A D | python3-flask-user_0.6.19.bb | 2 DESCRIPTION = "Customizable User Account Management for Flask; Register \
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| /openbmc/u-boot/arch/arm/mach-davinci/ |
| H A D | Kconfig | 79 Value written to PLLC0 PLL Post-Divider Control Register
127 Value written to PLLC1 PLL Post-Divider Control Register
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| /openbmc/qemu/hw/ufs/ |
| H A D | trace-events | 23 ufs_err_unsupport_register_offset(uint32_t offset) "Register offset 0x%"PRIx32" is not yet supporte…
24 ufs_err_invalid_register_offset(uint32_t offset) "Register offset 0x%"PRIx32" is invalid"
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| /openbmc/linux/Documentation/input/devices/ |
| H A D | sentelic.rst | 510 Programming Sequence for Register Reading/Writing
513 Register inversion requirement:
520 Register swapping requirement:
527 Register reading sequence:
546 swapped(refer to the 'Register swapping requirement' section),
572 Register writing sequence:
585 swapped(refer to the 'Register swapping requirement' section),
607 swapped(refer to the 'Register swapping requirement' section),
630 Programming Sequence for Page Register Reading/Writing
680 swapped(refer to the 'Register swapping requirement' section),
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/ata/ |
| H A D | ahci-da850.txt | 8 AHCI 1.1 standard and the Power Down Control Register (PWRDN)
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| /openbmc/libmctp/docs/bindings/ |
| H A D | vendor-ibm-astlpc.md | 33 A hardware-defined flag bit in a KCS device's Status Register (STR). The IBF
35 Input Data Register (IDR).
37 **IDR: Input Data Register**
72 A hardware-defined flag bit in a KCS device's Status Register (STR). The OBF
74 Output Data Register (ODR).
76 **ODR: Output Data Register**
81 **STR: Status Register**
134 The KCS hardware consists of two single-byte buffers: the Output Data Register
135 (ODR) and the Input Data Register (IDR). The ODR is written by the BMC and read
287 #### KCS Status Register Layout
[all …]
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| /openbmc/u-boot/arch/arm/mach-uniphier/arm32/ |
| H A D | psci_smp.S | 14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
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