| /openbmc/u-boot/board/freescale/m547xevb/ |
| H A D | README | 151 make M5475AFE_config, or - boot 2MB, RAM 64MB
152 make M5475BFE_config, or - boot 2MB, code 16MB, RAM 64MB
153 make M5475CFE_config, or - boot 2MB, code 16MB, Video, USB, RAM 64MB
154 make M5475DFE_config, or - boot 2MB, USB, RAM 64MB
155 make M5475EFE_config, or - boot 2MB, Video, USB, RAM 64MB
156 make M5475FFE_config, or - boot 2MB, code 32MB, Video, USB, RAM 128MB
157 make M5475GFE_config, or - boot 2MB, RAM 64MB
246 mtest - simple RAM test
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| /openbmc/linux/tools/testing/selftests/zram/ |
| H A D | README | 1 zram: Compressed RAM based block devices
5 The zram module creates RAM based block devices named /dev/zram<id>
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| /openbmc/u-boot/drivers/dfu/ |
| H A D | Kconfig | 39 bool "RAM back end for DFU"
41 This option enables using DFU to read and write RAM on the target.
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| /openbmc/u-boot/lib/optee/ |
| H A D | Kconfig | 18 hex "Amount of Trust-Zone RAM for the OPTEE image"
25 hex "Base address of Trust-Zone RAM for the OPTEE image"
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | xlnx,zynqmp-ocmc-1.0.yaml | 16 being written, the ECC is generated and written into the ECC RAM along with
17 the write-data that is written into the data RAM. If one or more bytes are
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| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | qcom,rpm-proc.yaml | 26 | | Code RAM |--| +------------------+ |
28 | +---------------+ |--| Message RAM | |
29 | | Data RAM |--| | | |
43 | +--------------------------+ | | Message RAM |
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| /openbmc/linux/arch/arm/mm/ |
| H A D | proc-arm740.S | 73 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
74 ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
81 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
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| /openbmc/u-boot/board/sunxi/ |
| H A D | README.nand | 31 Then, you'll need to first load an SPL to initialise the RAM:
34 Load the binaries we'll flash into RAM:
41 On your board, you'll now have all the needed binaries into RAM, so
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| /openbmc/linux/Documentation/devicetree/bindings/soc/qcom/ |
| H A D | qcom,aoss-qmp.yaml | 16 SoC has its own block of message RAM and IRQ for communication with the AOSS.
17 The protocol used to communicate in the message RAM is known as Qualcomm
46 The base address and size of the message RAM for this client's
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| /openbmc/qemu/docs/devel/migration/ |
| H A D | CPR.rst | 27 Guest RAM can be saved in place if backed by shared memory, or can be
33 the RAM is backed by persistent shared memory, such as a DAX device,
40 suspend to RAM. Beware that suspension can take a few seconds, so
47 It is recommended that guest RAM be backed with some type of shared
51 RAM is copied to the migration URI.
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| /openbmc/qemu/system/ |
| H A D | memory_ldst.c.inc | 44 /* RAM case */
113 /* RAM case */
179 /* RAM case */
217 /* RAM case */
322 /* RAM case */
384 /* RAM case */
418 /* RAM case */
482 /* RAM case */
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| /openbmc/u-boot/doc/ |
| H A D | README.POST | 93 1) Tests running before relocating to RAM
95 These tests will run immediately after initializing RAM
100 2) Tests running after relocating to RAM
122 #define POST_RAM 0x200 /* test runs in RAM */
134 otherwise all tests running in ROM/RAM (depending on the flag
238 save it in non-volatile RAM (NVRAM), transfer it to a dedicated
409 This test will examine RAM and check it for errors. The test
411 amount of RAM will be checked. On power-fail booting a fool
633 of RAM around each 1Mb boundary. For example, for 64Mb RAM the
637 whole RAM.
[all …]
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| H A D | README.falcon | 18 required initialization. SPL mainly initializes the RAM controller, and then
62 CONFIG_SYS_SPL_ARGS_ADDR Address in RAM where the parameters must be
116 or prepared FDT) from temporary storage in RAM into persistant storage
121 RAM address of temporary storage. The RAM address of FDT will also be
162 Now the kernel is in RAM at address 0x82000000
176 Argument image is now in RAM at: 0x80000100
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| H A D | README.memory-test | 29 - It is terribly slow. Running "mtest" on the whole system RAM
43 test basically the whole system RAM, with only exempting the
86 controller), varying RAM use, etc. to trigger any weak spots in this
95 Note 2: Ironically enough, the "test_burst" did not catch any RAM
97 to catch did not happen when accessing the RAM, but when reading from
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.falcon | 4 RAM version U-Boot. Instead, it loads FIT image and boot directly to Linux.
19 A command "spl export" should be called under the normal RAM version U-Boot.
135 NAND boot, a RAM version full feature U-Boot is needed. Unlike SD or NAND boot,
136 SPL with QSPI doesn't need to combine SPL image with RAM version image. Two
138 image with RCW and PBI commands to load the SPL payload into On-Chip RAM. The
139 latter is RAM version U-Boot in FIT format (or legacy format if FIT is not
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| /openbmc/linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,pruss.yaml | 18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
40 RAM, and specific register spaces for Control and Debug functionalities.
106 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
111 Address and size of the Shared Data RAM. Note that on AM437x one
112 of two PRUSS units don't contain Shared RAM, while the second one
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| /openbmc/linux/arch/sh/include/mach-ecovec24/mach/ |
| H A D | partner-jet-setup.txt | 6 LIST "zImage (RAM boot)"
7 LIST "This script can be used to boot the kernel from RAM via JTAG:"
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| /openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/ |
| H A D | i2c.txt | 8 Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | silabs,si570.txt | 31 - silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely
32 on hardware loading of RAM from NVM at power on.
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| /openbmc/linux/Documentation/devicetree/bindings/soc/loongson/ |
| H A D | loongson,ls2k-pmc.yaml | 35 RAM) firmware entry address which was jumped from kernel and it's
38 SoC whether support Suspend To RAM.
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-zynqmp-fpga | 30 BIT(6) 0: Flip-flops and block RAM are write disabled
31 1: Flip-flops and block RAM are write enabled
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| /openbmc/linux/drivers/gpu/drm/ci/xfails/ |
| H A D | amdgpu-stoney-skips.txt | 1 # Suspend to RAM seems to be broken on this machine
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| /openbmc/linux/Documentation/networking/device_drivers/atm/ |
| H A D | iphase.rst | 93 The (i)Chip boards have 3 different packet RAM size variants: 128K, 512K and
94 1M. The RAM size decides the number of buffers and buffer size. The default
98 Total Rx RAM Tx RAM Rx Buf Tx Buf Rx buf Tx buf
99 RAM size size size size size cnt cnt
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| /openbmc/u-boot/arch/xtensa/cpu/ |
| H A D | u-boot.lds | 17 * U-Boot resets from SYSROM and unpacks itself from a ROM store to RAM.
26 * we can simplify the boot process and unpack U-Boot to RAM immediately.
91 * On many Xtensa boards a region of RAM may be mapped to the ROM address
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | nvidia,tegra210-adx.yaml | 12 channels each. A byte RAM helps to form output frames by any combination
14 RAM in the AMX except that the data flow direction is reversed.
|