Searched refs:Memory (Results 51 – 75 of 811) sorted by relevance
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7 title: Arm PL35x Series Static Memory Controller (SMC)13 The PL35x Static Memory Controller is a bus where you can connect two kinds69 - description: Combined or Memory interface 0 IRQ70 - description: Memory interface 1 IRQ
7 title: NVIDIA Tegra20 SoC External Memory Controller15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to16 service the request stream sent from Memory Controller. The EMC also has46 Phandle of the Memory Controller node.72 Memory clock rate in kHz.
7 title: NVIDIA Tegra124 SoC Memory Controller16 two memory channels. The Tegra124 Memory Controller handles memory requests61 Memory clock rate in Hz.
147 | CPU 1 |<----->| Memory |<----->| CPU 2 |2905 Chapter 7.1: Memory-Access Ordering2914 Chapter 7.2: Memory Ordering2918 Chapter 8: Memory Models2926 Chapter 15: Sparc-V9 Memory Models2929 Chapter 9: Memory Models2932 Chapter 8: Memory Models2935 Chapter 9: Memory2939 Chapter 8: Memory Models2948 Chapter 13: Other Memory Models[all …]
39 - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)55 Memory map from core's view76 0x5_1000_0000..0x5_1fff_ffff Memory Hole88 Memory map for NOR boot113 Memory map for QSPI flash
2 …XX","XX","XX","0x02","0x01","Chassis Number","Failed Memory Card","Spare Memory Card","0x00","Memo…3 …XX","XX","XX","0x02","0x04","Chassis Number","Memory Card","Completion Code (0x00=Success)","0x00"…4 …"XX","XX","XX","0x02","0x05","Chassis Number","Memory Card","Memory Size (in 512MB units)","0x00",…72 "0xE0","0x02","0x00","Chassis Number","Memory Card","Memory DIMM","R","R","R","R","R","R","R","0x00…74 "0xE0","0x02","0x02","0x00","Chassis","Memory Card","Memory DIMM","R","R","R","R","R","R","0x00","D…75 "0xE0","0x02","0x02","0x01","Chassis","Memory Card","Memory DIMM","R","R","R","R","R","R","0x00","D…77 "0xE0","0x02","0x02","0x03","Chassis","Memory Card","Memory DIMM","R","R","R","R","R","R","0x00","D…79 "0xE0","0x02","0x03","0x00","Chassis Number","Memory Card","R","R","R","R","R","R","R","0x00","Memo…80 "0xE0","0x02","0x03","0x01","Chassis Number","Memory Card","R","R","R","R","R","R","R","0x00","Memo…81 "0xE0","0x02","0x00","0x00","Chassis","Memory Card","Memory DIMM","R","R","R","R","R","R","0x01","D…[all …]
16 * Memory devices23 * Memory Stick28 called DIMM (Dual Inline Memory Module).30 * Memory Socket73 it from the Memory Controller.109 * High Bandwidth Memory (HBM)120 Memory Controllers123 Most of the EDAC core is focused on doing Memory Controller error detection.199 and each GPU data fabric contains four Unified Memory Controllers (UMC).207 Memory controllers on AMD GPU nodes can be represented in EDAC thusly:[all …]
158 …| Memory's CE | /sys/bus/platform/devices/smpro-errmon.*/error_mem_ce | Memory has CE error …160 …| Memory's UE | /sys/bus/platform/devices/smpro-errmon.*/error_mem_ue | Memory has UE error …196 …| Memory's CE | /sys/bus/platform/devices/smpro-errmon.*/overflow_mem_ce | Memory CE error overfl…198 …| Memory's UE | /sys/bus/platform/devices/smpro-errmon.*/overflow_mem_ue | Memory UE error overfl…265 For more details, see section `5.7 GPI Status Registers and 5.9 Memory Error Register Definitions,
5 tristate "STM32 Digital Camera Memory Interface (DCMI) support"13 This module makes the STM32 Digital Camera Memory Interface (DCMI)
16 Itanium Processor Family Memory Ordering". Intel Corporation.104 Alan Stern. 2017-2019. "A Formal Model of Linux-Kernel Memory109 Memory-model tooling118 Memory". ACM Trans. Program. Lang. Syst. 36, 2, Article 7 (July126 Memory-model comparisons130 Feng. 2018. "Linux-Kernel Memory Model". (27 September 2018).
38 Q6INSN(Y2_isync,"isync",ATTRIBS(),"Memory Synchronization",{fISYNC();})39 Q6INSN(Y2_barrier,"barrier",ATTRIBS(A_RESTRICT_SLOT0ONLY),"Memory Barrier",{fBARRIER();})40 Q6INSN(Y2_syncht,"syncht",ATTRIBS(A_RESTRICT_SLOT0ONLY),"Memory Synchronization",{fSYNCH();})
6 Video Memory-To-Memory Interface23 Memory-to-memory devices function as a shared resource: you can
49 - :cspan:`4` Memory100 - :cspan:`4` Memory125 - :cspan:`4` Memory150 - :cspan:`4` Memory
10 tristate "Virtual Memory-to-Memory Driver"
2 Memory Hot(Un)Plug38 Memory Hot(Un)Plug Granularity53 Phases of Memory Hotplug56 Memory hotplug consists of two phases:70 Phases of Memory Hotunplug85 Memory Hotplug Notifications136 Onlining and Offlining Memory Blocks151 Onlining Memory Blocks Manually214 Offlining Memory Blocks263 Configuring Memory Hot(Un)Plug[all …]
75 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and146 description: GPU Memory clock148 description: GPU Memory Interface clock150 description: GPU Alternative Memory Interface clock184 description: GPU Memory Interface clock186 description: GPU Alternative Memory Interface clock
39 Memory, enumerator70 Memory, enumerator
20 Memory subsystem23 - Memory subsyetem soft-error protection
7 title: Amazon's Annapurna Labs Memory Controller EDAC15 Amazon's Annapurna Labs Memory Controller.
34 Processor and Memory Bus Initialization37 Memory Initialization
2 Memory Management Documentation5 Memory Management Guide
72 "Memory Operating Speed Selection",73 "Force specific Memory Operating Speed or use Auto setting.",74 "Advanced/Memory Configuration/Memory Operating Speed Selection",
46 Graphic Memory Controller49 GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple93 Memory Queue Descriptor
6 # Memory constants7 option('memory-region-size', type: 'integer', value: 16384, description: 'Memory size allcated')
1 SUMMARY = "Persistent Memory Development Kit"2 DESCRIPTION = "Persistent Memory Development Kit"