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/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A Dl1tf.rst1 L1TF - L1 Terminal Fault
4 L1 Terminal Fault is a hardware vulnerability which allows unprivileged
38 CVE-2018-3615 L1 Terminal Fault SGX related aspects
39 CVE-2018-3620 L1 Terminal Fault OS, SMM related aspects
40 CVE-2018-3646 L1 Terminal Fault Virtualization related aspects
97 share the L1 Data Cache (L1D) is important for this. As the flaw allows
/openbmc/linux/arch/powerpc/boot/dts/
H A Dtqm8548-bigflash.dts38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
H A Dtqm8548.dts38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
H A Dkmeter1.dts36 d-cache-size = <32768>; // L1, 32K
37 i-cache-size = <32768>; // L1, 32K
H A Dxpedite5200_xmon.dts41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
H A Dmpc5121.dtsi33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc50 /* ??? Odd man out. The L1 field here is really a register, but the
/openbmc/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g4.c1489 #define L1 180 macro
1490 SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
1491 SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4);
1492 PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4));
1493 FUNC_GROUP_DECL(ADC4, L1);
2047 ASPEED_PINCTRL_PIN(L1),
2500 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8),
2501 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8),
/openbmc/linux/arch/alpha/lib/
H A Dev6-clear_user.S139 wh64 ($3) # .. .. .. L1 : memory subsystem hint
H A Dev6-memcpy.S85 wh64 ($7) # L1 : memory subsystem hint: 64 bytes at
/openbmc/qemu/tests/qemu-iotests/
H A D206.out190 Job failed: Could not resize image: Failed to grow the L1 table: File too large
250 Job failed: Could not resize image: Failed to grow the L1 table: File too large
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml44 Each processor includes separate L1 instruction and data caches and
/openbmc/qemu/docs/system/i386/
H A Dhyperv.rst162 implements paravirtualized protocol between L0 (KVM) and L1 (Hyper-V)
230 enabled, it allows L0 (KVM) and L1 (Hyper-V) hypervisors to collaborate to
251 guest without the need to exit to L1 (Hyper-V) hypervisor. While the feature is
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dpci.txt34 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5200.txt180 of three cells; <L1 L2 level>
182 L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-usb276 L1 sleep state. The usb2_lpm_l1_timeout attribute allows
277 tuning the timeout for L1 inactivity timer (LPM timer), e.g.
278 needed inactivity time before host requests the device to go to L1 sleep.
287 L1 sleep state now use a best effort service latency value (BESL) to
/openbmc/qemu/disas/
H A Dmips.c1187 #define L1 INSN_4010 macro
2247 {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 },
2248 {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
2249 {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
2250 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
2621 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
2634 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
2882 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2883 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
3058 {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsleep44xx.S75 mov r1, #0xFF @ clean seucre L1
H A DKconfig263 bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
/openbmc/qemu/docs/
H A Dimage-fuzzer.txt28 elements, e.g. L1/L2 tables, having random invalid values.
128 The generator can create header fields, header extensions, L1/L2 tables and
/openbmc/linux/Documentation/staging/
H A Dcrc32.rst134 more importantly, too much of the L1 cache.
174 be kept busy and make full use of its L1 cache.
/openbmc/linux/Documentation/devicetree/bindings/arm/msm/
H A Dqcom,idle-state.txt44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6375-sony-xperia-murray-pdx225.dts211 * L1 is VDD_LPI_CX
/openbmc/qemu/tests/qemu-iotests/sample_images/
H A Diotest-dirtylog-10G-4M.vhdx.bz21vhdxfileQ�E�M�U� �v�1�.�6�.�5�
/openbmc/linux/arch/arm/mm/
H A Dproc-macros.S271 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line

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