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Searched refs:CONFIG_SYS_CLK_FREQ (Results 51 – 75 of 178) sorted by relevance

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/openbmc/u-boot/include/configs/
H A DMPC8349EMDS.h33 #ifndef CONFIG_SYS_CLK_FREQ
35 #define CONFIG_SYS_CLK_FREQ 66000000 macro
38 #define CONFIG_SYS_CLK_FREQ 33000000 macro
H A Dls1088aqds.h45 #define CONFIG_SYS_CLK_FREQ 100000000 macro
50 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() macro
54 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
H A Drcar-gen2-common.h64 #define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 8)
H A Dblanche.h52 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK macro
H A Dsmdkc100.h27 #define CONFIG_SYS_CLK_FREQ 12000000 macro
H A Dlegoev3.h21 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) macro
H A Dti816x_evm.h40 #define CONFIG_SYS_CLK_FREQ 27000000 macro
H A Dls2080a_emu.h11 #define CONFIG_SYS_CLK_FREQ 100000000 macro
H A Dqemu-ppce500.h60 #define CONFIG_SYS_CLK_FREQ 33000000 macro
H A Dcyrus.h30 #define CONFIG_SYS_CLK_FREQ 133000000 macro
33 #define CONFIG_SYS_CLK_FREQ 100000000 macro
H A DMPC8323ERDB.h24 #ifndef CONFIG_SYS_CLK_FREQ
25 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN macro
/openbmc/u-boot/configs/
H A Dnsim_700_defconfig6 CONFIG_SYS_CLK_FREQ=70000000
H A Dnsim_700be_defconfig7 CONFIG_SYS_CLK_FREQ=70000000
H A Dnsim_hs38_defconfig7 CONFIG_SYS_CLK_FREQ=70000000
H A Dnsim_hs38be_defconfig8 CONFIG_SYS_CLK_FREQ=70000000
H A Dtb100_defconfig5 CONFIG_SYS_CLK_FREQ=500000000
H A DA10-OLinuXino-Lime_defconfig7 CONFIG_SYS_CLK_FREQ=912000000
H A Demsdp_defconfig7 CONFIG_SYS_CLK_FREQ=40000000
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch2_speed.c49 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; in get_sys_info()
54 #define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ in get_sys_info()
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dspl_minimal.c30 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
/openbmc/u-boot/board/Arcturus/ucp1020/
H A Dspl_minimal.c34 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
/openbmc/u-boot/board/freescale/c29xpcie/
H A Dspl_minimal.c30 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dspl_minimal.c31 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
/openbmc/u-boot/board/renesas/eagle/
H A Deagle.c49 stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET; in s_init()
/openbmc/u-boot/drivers/clk/
H A Dmpc83xx_clk.h319 return CONFIG_SYS_CLK_FREQ / (1 + clkin_div); in get_pci_sync_in()
333 return CONFIG_SYS_CLK_FREQ * spmf; in get_csb_clk()

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