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Searched refs:SMP (Results 101 – 125 of 275) sorted by relevance

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/openbmc/linux/Documentation/translations/zh_CN/core-api/
H A Dcachetlb.rst28 为SMP，则只需将定义简单地扩展一下，使发生在某个特定接口的副作用扩展到系
29 统的所有处理器上。不要被这句话吓到，以为SMP的缓存/tlb刷新一定是很低
/openbmc/linux/arch/powerpc/
H A DKconfig112 depends on SMP && PREEMPTION && !PPC_QUEUED_SPINLOCKS
193 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
352 default y if PPC32 && SMP
527 depends on SMP
570 depends on SMP && (PPC_PSERIES || \
574 CPUs at runtime on SMP machines.
589 depends on SMP
607 def_bool PPC_BOOK3S || PPC_E500 || (44x && !SMP)
724 depends on SMP
733 depends on PPC64 && SMP
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/openbmc/linux/Documentation/translations/ko_KR/
H A Dstable_api_nonsense.txt82 non-SMP 빌드에서는 사라져 버릴수도 있다).
/openbmc/linux/drivers/accessibility/speakup/
H A DTODO11 It seems to only happen on SMP systems. It seems that text in the output buffer
/openbmc/linux/arch/alpha/
H A DKconfig23 select AUTO_IRQ_AFFINITY if SMP
298 AlphaServer ES45/DS25 SMP based on EV68 and Titan chipset.
303 AlphaServer GS 40/80/160/320 SMP based on the EV67 core.
516 config SMP config
530 See also the SMP-HOWTO available at
538 depends on SMP
556 default y if SMP
570 For SMP systems we cannot use the cycle counter for timing anyway,
/openbmc/linux/Documentation/core-api/
H A Dgenericirq.rst46 In the SMP world of the __do_IRQ() super-handler another type was
138 - disable_irq_nosync() (SMP only)
140 - synchronize_irq() (SMP only)
292 Per CPU interrupts are only available on SMP and the handler provides a
382 Locking on SMP
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-dt.txt4 both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share
/openbmc/linux/Documentation/arch/ia64/
H A Dia64.rst47 * SMP locks cleanup/optimization
/openbmc/linux/drivers/cpuidle/
H A DKconfig.arm100 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
114 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmarvell,armada-370-xp-mpic.txt14 interrupt registers. For this last pair, to be compliant with SMP
H A Dsnps,archs-idu-intc.txt3 This optional 2nd level interrupt controller can be used in SMP configurations
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Drenesas,apmu.yaml15 CPU core power domain control including SMP boot and CPU Hotplug.
/openbmc/linux/arch/arm/mach-sunxi/
H A DKconfig64 depends on SMP
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dsram.yaml181 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
207 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
282 // cpu0 should jump to SMP entry vector
/openbmc/linux/arch/riscv/
H A DKconfig71 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
77 select GENERIC_IRQ_IPI if SMP
78 select GENERIC_IRQ_IPI_MUX if SMP
353 config SMP config
368 depends on SMP
376 depends on SMP
385 depends on SMP
406 depends on SMP && MMU
652 depends on SMP
676 select HOTPLUG_CPU if SMP
/openbmc/linux/arch/arm/include/asm/
H A Dspinlock.h6 #error SMP not supported on pre-ARMv6 CPUs
H A Dcmpxchg.h78 #error SMP is not supported on this platform in __arch_xchg()
/openbmc/linux/arch/arm/mm/
H A DKconfig389 select SMP_ON_UP if SMP
452 select TLS_REG_EMUL if SMP || !MMU
459 select TLS_REG_EMUL if SMP || !MMU
466 select TLS_REG_EMUL if SMP || !MMU
473 select TLS_REG_EMUL if SMP || !MMU
719 bool "Emulate SWP/SWPB instructions" if !SMP
721 default y if SMP
803 depends on SMP && CPU_V7
811 depends on (CPU_CP15 && !SMP) || CPU_V7M
887 An SMP system using a pre-ARMv6 processor (there are apparently
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dstericsson,u8500-clks.yaml17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
102 description: A subnode for the ARM SMP Timer Watchdog cluster with zero
/openbmc/linux/drivers/tty/hvc/
H A DKconfig92 depends on SMP && HVC_DCC
101 In SMP mode, external debuggers create multiple windows, and each window
/openbmc/linux/Documentation/translations/ja_JP/
H A Dstable_api_nonsense.txt108 （例：SMP向けではないビルドでは、いくつかのロックは中身が
/openbmc/linux/arch/arm/mach-tegra/
H A Dsleep.h91 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
/openbmc/qemu/docs/system/openrisc/
H A Dvirt.rst19 * SMP (OpenRISC multicore using ompic)
/openbmc/qemu/docs/system/
H A Dtarget-sparc.rst27 The emulation is somewhat complete. SMP up to 16 CPUs is supported, but
/openbmc/u-boot/doc/device-tree-bindings/mailbox/
H A Dnvidia,tegra186-hsp.txt7 two processors not in an SMP relationship.

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