irqchip: Add Kconfig symbols for sunxi drivers

Not all of these drivers are needed on every ARCH_SUNXI platform. In
particular, the ARCH_SUNXI symbol will be reused for the Allwinner D1,
a RISC-V So

irqchip: Add Kconfig symbols for sunxi drivers

Not all of these drivers are needed on every ARCH_SUNXI platform. In
particular, the ARCH_SUNXI symbol will be reused for the Allwinner D1,
a RISC-V SoC which contains none of these irqchips.

Introduce Kconfig symbols so we can select only the drivers actually
used by a particular set of platforms. This also lets us move the
irqchip driver dependencies to a more appropriate location.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220509034941.30704-1-samuel@sholland.org

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ARM: rework endianess selection

Choosing big-endian vs little-endian kernels in Kconfig has not worked
correctly since the introduction of CONFIG_ARCH_MULTIPLATFORM a long
time ago.

The problems is

ARM: rework endianess selection

Choosing big-endian vs little-endian kernels in Kconfig has not worked
correctly since the introduction of CONFIG_ARCH_MULTIPLATFORM a long
time ago.

The problems is that CONFIG_BIG_ENDIAN depends on
ARCH_SUPPORTS_BIG_ENDIAN, which can set by any one platform
in the config, but would actually have to be supported by all
of them.

This was mostly ok for ARMv6/ARMv7 builds, since these are BE8 and
tend to just work aside from problems in nonportable device drivers.
For ARMv4/v5 machines, CONFIG_BIG_ENDIAN and CONFIG_ARCH_MULTIPLATFORM
were never set together, so this was disabled on all those machines
except for IXP4xx.

As IXP4xx can now become part of ARCH_MULTIPLATFORM, it seems better to
formalize this logic: all ARMv4/v5 platforms get an explicit dependency
on being either big-endian (ixp4xx) or little-endian (the rest). We may
want to fix ixp4xx in the future to support both, but it does not work
in LE mode at the moment.

For the ARMv6/v7 platforms, there are two ways this could be handled

a) allow both modes only for platforms selecting
'ARCH_SUPPORTS_BIG_ENDIAN' today, but only LE mode for the
others, given that these were added intentionally at some
point.

b) allow both modes everwhere, given that it was already possible
to build that way by e.g. selecting ARCH_VIRT, and that the
list is not an accurate reflection of which platforms may or
may not work.

Out of these, I picked b) because it seemed slighly more logical
to me.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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irqchip/sun6i-r: Use a stacked irqchip driver

The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
original sun4i interrupt controller than the sun7i/sun9i NMI controller.
It is

irqchip/sun6i-r: Use a stacked irqchip driver

The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
original sun4i interrupt controller than the sun7i/sun9i NMI controller.
It is used for two distinct purposes:
- To control the trigger, latch, and mask for the NMI input pin
- To provide the interrupt input for the ARISC coprocessor

As this interrupt controller is not documented, information about it
comes from vendor-provided firmware blobs and from experimentation.

Differences from the sun4i interrupt controller appear to be:
- It only has one or two registers of each kind (max 32 or 64 IRQs)
- Multiplexing logic is added to support additional inputs
- There is no FIQ-related logic
- There is no interrupt priority logic

In order to fulfill its two purposes, this hardware block combines four
types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this
chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0
pending" output from this chip, if enabled, is then routed to a SPI IRQ
input on the GIC. In other words, bit 0 of IRQ_ENABLE_REG *does* affect
the NMI IRQ seen at the GIC.

The NMI is followed by a contiguous block of 15 "direct" (my name for
them) IRQ inputs that are connected in parallel to both R_INTC and the
GIC. Or in other words, these bits of IRQ_ENABLE_REG *do not* affect the
IRQs seen at the GIC.

Following the direct IRQs are the ARISC's copy of banked IRQs for shared
peripherals. These are not relevant to Linux. The remaining IRQs are
connected to a multiplexer and provide access to the first (up to) 128
SPIs from the ARISC. This range of SPIs overlaps with the direct IRQs.

Because of the 1:1 correspondence between R_INTC and GIC inputs, this is
a perfect scenario for using a stacked irqchip driver. We want to hook
into setting the NMI trigger type, but not actually handle any IRQ here.

To allow access to all multiplexed IRQs, this driver requires a new
binding where the interrupt number matches the GIC interrupt number.
(This moves the NMI from number 0 to 32 or 96, depending on the SoC.)
For simplicity, copy the three-cell GIC binding; this disambiguates
interrupt 0 in the old binding (the NMI) from interrupt 0 in the new
binding (SPI 0) by the number of cells.

Since R_INTC is in the always-on power domain, and its output is visible
to the power management coprocessor, a stacked irqchip driver provides a
simple way to add wakeup support to any of its IRQs. That is the next
patch; for now, just the NMI is moved over.

This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi:
Support sun6i-a31-r-intc compatible").

Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210118055040.21910-4-samuel@sholland.org

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treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project

treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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ARM: sunxi: add Allwinner ARMv5 SoCs

Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die
used for many new F-series products, including F1C100A, F1C100s, F1C200s,
F1C500, F1C600).

ARM: sunxi: add Allwinner ARMv5 SoCs

Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die
used for many new F-series products, including F1C100A, F1C100s, F1C200s,
F1C500, F1C600).

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs

Allwinner also has some ARMv5 SoCs.

In order to add support for them, check ARM_MULTI_V7 before enabling
ARMv7 SoC's. Add help text

ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs

Allwinner also has some ARMv5 SoCs.

In order to add support for them, check ARM_MULTI_V7 before enabling
ARMv7 SoC's. Add help text for ARCH_SUNXI menuconfig.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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ARM: sun8i: smp: Add support for A83T

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allw

ARM: sun8i: smp: Add support for A83T

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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ARM: sun9i: Support SMP bring-up on A80

The A80 is a big.LITTLE SoC with 1 cluster of 4 Cortex-A7s and
1 cluster of 4 Cortex-A15s.

This patch adds support to bring up the second cluster and thus al

ARM: sun9i: Support SMP bring-up on A80

The A80 is a big.LITTLE SoC with 1 cluster of 4 Cortex-A7s and
1 cluster of 4 Cortex-A15s.

This patch adds support to bring up the second cluster and thus all
cores using custom platform SMP code. Core/cluster power down has not
been implemented, thus CPU hotplugging is not supported.

Parts of the trampoline and re-entry code for the boot cpu was adapted
from the MCPM framework.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>

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ARM: sunxi: Select PM_OPP

Device frequency scaling is implemented through devfreq in the kernel,
which requires CONFIG_PM_OPP.

Let's select it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-ele

ARM: sunxi: Select PM_OPP

Device frequency scaling is implemented through devfreq in the kernel,
which requires CONFIG_PM_OPP.

Let's select it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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ARM: sunxi: enable big-endian

With previous fixes to stmmac, sun4i-emac and sun4i-mmc at least the
Cubieboard2 incarnation of sunxi works correctly in big-endian mode.
Allow the selection of big-end

ARM: sunxi: enable big-endian

With previous fixes to stmmac, sun4i-emac and sun4i-mmc at least the
Cubieboard2 incarnation of sunxi works correctly in big-endian mode.
Allow the selection of big-endian.

Tested using a Cubieboard2 DualCard and the following
hardware-components:
- GMAC (stmmac)
- EMAC (sun4i-emac)
- SATA
- SPI
- UART
- security system
- touchscreen controller hwmon functionality
- pinctrl (custom interrupt for SPI ethernet controller)
- watchdog as reset controller
- onboard RTC
- DS1307 I2C RTC
- sound codec and with this indirectly the DMA engine

Signed-off-by: Michael Weiser <michael.weiser@gmx.de>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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ARM: do away with ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB

This replaces:

- "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB" as this can
now be selected directly.

- "select ARCH_WANT_OPTIONAL_GPI

ARM: do away with ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB

This replaces:

- "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB" as this can
now be selected directly.

- "select ARCH_WANT_OPTIONAL_GPIOLIB" with no dependency: GPIOLIB
is now selectable by everyone, so we need not declare our
intent to select it.

When ordering the symbols the following rationale was used:
if the selects were in alphabetical order, I moved select GPIOLIB
to be in alphabetical order, but if the selects were not
maintained in alphabetical order, I just replaced
"select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB".

Cc: Michael Büsch <m@bues.ch>
Cc: arm@kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

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ARM: use "depends on" for SoC configs instead of "if" after prompt

Many ARM sub-architectures use prompts followed by "if" conditional,
but it is wrong.

Please notice the difference between

co

ARM: use "depends on" for SoC configs instead of "if" after prompt

Many ARM sub-architectures use prompts followed by "if" conditional,
but it is wrong.

Please notice the difference between

config ARCH_FOO
bool "Foo SoCs" if ARCH_MULTI_V7

and

config ARCH_FOO
bool "Foo SoCs"
depends on ARCH_MULTI_V7

These two are *not* equivalent!

In the former statement, it is not ARCH_FOO, but its prompt that
depends on ARCH_MULTI_V7. So, it is completely valid that ARCH_FOO
is selected by another, but ARCH_MULTI_V7 is still disabled. As it is
not unmet dependency, Kconfig never warns. This is probably not what
you want.

The former should be used only when you need to do so, and you really
understand what you are doing. (In most cases, it should be wrong!)

For enabling/disabling sub-architectures, the latter is always correct.

As a good side effect, this commit fixes some entries over 80 columns
(mach-imx, mach-integrator, mach-mbevu).

[Arnd: I note that there is not really a bug here, according to
the discussion that followed, but I can see value in being consistent
and in making the lines shorter]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Krzysztof Halasa <khc@piap.pl>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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ARM: sunxi: Introduce Allwinner H3 support

The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar
to other sun8i family SoCs like the A23.

Signed-off-by: Jens Kuske <jenskuske@gmai

ARM: sunxi: Introduce Allwinner H3 support

The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar
to other sun8i family SoCs like the A23.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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ARM: sunxi: Have ARCH_SUNXI select RESET_CONTROLLER for clock driver usage

As the sunxi usb clocks all contain a reset controller, it is not
possible to build the sunxi clock driver without RESET_CO

ARM: sunxi: Have ARCH_SUNXI select RESET_CONTROLLER for clock driver usage

As the sunxi usb clocks all contain a reset controller, it is not
possible to build the sunxi clock driver without RESET_CONTROLLER
enabled. Doing so results in an undefined symbol error:

drivers/built-in.o: In function `sunxi_gates_clk_setup':
linux/drivers/clk/sunxi/clk-sunxi.c:1071: undefined reference to
`reset_controller_register'

This is possible if building a minimal kernel without PHY_SUN4I_USB.

The dependency issue is made visible at compile time instead of
link time by the new A80 mmc clocks, which also use a reset control
itself.

This patch makes ARCH_SUNXI select ARCH_HAS_RESET_CONTROLLER and
RESET_CONTROLLER.

Fixes: 559482d1f950 ARM: sunxi: Split the various SoCs support in Kconfig
Cc: <stable@vger.kernel.org> # 3.16+
Reported-by: Lourens Rozema <ik@lourensrozema.nl>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER for sun9i

The A80 SoC has reset controls matching bus clock gates.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxim

ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER for sun9i

The A80 SoC has reset controls matching bus clock gates.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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ARM: sunxi: Introduce Allwinner A80 support

The Allwinner A80 is a new Cortex octo-core A7/A15 big.LITTLE SoC.
While it's processor cores and interconnecting bus are new, it
re-uses many peripherals

ARM: sunxi: Introduce Allwinner A80 support

The Allwinner A80 is a new Cortex octo-core A7/A15 big.LITTLE SoC.
While it's processor cores and interconnecting bus are new, it
re-uses many peripherals found in earlier Allwinner SoCs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Andreas Färber <afaerber@suse.de>

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pinctrl: sunxi: Remove PINCTRL_SUNXI

The PINCTRL_SUNXI configuration was kept only to deal with the introduction of
per-machine symbols and the various pintrl drivers through different tree.

Now th

pinctrl: sunxi: Remove PINCTRL_SUNXI

The PINCTRL_SUNXI configuration was kept only to deal with the introduction of
per-machine symbols and the various pintrl drivers through different tree.

Now that it's not useful anymore, we can just remove it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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ARM: sunxi: select MFD_SUN6I_PRCM when sun8i arch support is enabled

Select the MFD_SUN6I_PRCM option when sun8i arch is enabled in order to
get the PRCM (Power/Reset/Clock Management) related drive

ARM: sunxi: select MFD_SUN6I_PRCM when sun8i arch support is enabled

Select the MFD_SUN6I_PRCM option when sun8i arch is enabled in order to
get the PRCM (Power/Reset/Clock Management) related drivers compiled.

Also select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER to make sure
the reset controller drivers are compiled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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ARM: sunxi: Introduce Allwinner A23 support

The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.

Signed-off-by: Chen-Yu Tsai <we

ARM: sunxi: Introduce Allwinner A23 support

The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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ARM: sunxi: select MFD_SUN6I_PRCM when sun6i arch support is enabled

Select the MFD_SUN6I_PRCM option when sun6i arch is enabled in order to get
the PRCM (Power/Reset/Clock Management) related drive

ARM: sunxi: select MFD_SUN6I_PRCM when sun6i arch support is enabled

Select the MFD_SUN6I_PRCM option when sun6i arch is enabled in order to get
the PRCM (Power/Reset/Clock Management) related drivers compiled.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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ARM: sunxi: Split the various SoCs support in Kconfig

This will allow to better isolate various options, and reduce the overall
kernel size if we're interested in only one of the SoCs.

Signed-off-b

ARM: sunxi: Split the various SoCs support in Kconfig

This will allow to better isolate various options, and reduce the overall
kernel size if we're interested in only one of the SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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ARM: sunxi: Select HAVE_ARM_ARCH_TIMER

In order for the architected timers support to be enabled in the kernel, this
option has to be enabled. Otherwise, the architected timers driver won't be
compi

ARM: sunxi: Select HAVE_ARM_ARCH_TIMER

In order for the architected timers support to be enabled in the kernel, this
option has to be enabled. Otherwise, the architected timers driver won't be
compiled in, and we will not get to use them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>

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ARM: select HAVE_SMP for V7 multi-platform

All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7
multi-platform builds.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Step

ARM: select HAVE_SMP for V7 multi-platform

All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7
multi-platform builds.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

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ARM: centralize common multi-platform kconfig options

Multi-platform requires various kconfig options to be selected, so
platforms don't need to select them individually.

Signed-off-by: Rob Herring

ARM: centralize common multi-platform kconfig options

Multi-platform requires various kconfig options to be selected, so
platforms don't need to select them individually.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>

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ARM: sunxi: select ARM_PSCI

On Allwinner sun7i (A20) SoCs, the SMP operations are implemented in
u-boot, and exposed to the kernel through PSCI.

We thus need to enable PSCI support for Allwinner So

ARM: sunxi: select ARM_PSCI

On Allwinner sun7i (A20) SoCs, the SMP operations are implemented in
u-boot, and exposed to the kernel through PSCI.

We thus need to enable PSCI support for Allwinner SoCs so that the
kernel uses it to bring up the additionnal cores.

Signed-off-by: Signed-off-by: Zalan Blenessy <zalan.blenessy@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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